Mismatch compensation in an analog-to-digital converter using reference path reconfiguration

Patent metadata

Field	Value
Publication number	US-10587283-B1
Application number	US-201816236690-A
Country	US
Kind code	B1
Filing date	Dec 31, 2018
Priority date	Dec 31, 2018
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) including a quantizer to receive an analog signal input and to provide a quantizer output, the quantizer comprising:
a linear-feedback shift register (LFSR) providing a LFSR output;
a decoder connected to the LFSR, the decoder having a plurality of decoder outputs, each decoder output to provide a switch control signal responsive to a LFSR value of the LFSR output;
an electrical reference having a plurality of reference outputs, each reference output to provide a reference level signal;
a plurality of switches, each switch having an input, a first switch output and a second switch output, the switch input connected to a first one of the decoder outputs to receive a first one of the switch control signals, the first switch output connected to a first one of the reference outputs when the first switch control signal is in a first state and connected to a second one of reference outputs when the first switch control signal is in a second state, and the second switch output connected to the second reference output when the first control signal is in the first state and connected to the first reference output when the first control signal is in the second state, wherein the input of each one of the plurality of switches is connected to a different one of the plurality of decoder outputs; and
a plurality of comparators, each comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output of an associated one of the plurality of switches, and the second reference input connected to the second switch output of the associated switch.

2. The ADC of claim 1 wherein the decoder comprises:
a mode selection input, the mode selection input configured to receive a mode selection value, wherein each decoder output further provides the switch control signal responsive to the mode selection value.

3. The ADC of claim 2 wherein the decoder selects a number of switch control signals to assert based upon the mode selection value.

4. The ADC of claim 2 wherein each switch control signal is asserted based upon an associated bit of the LSFR value when the mode selection value indicates a particular value.

5. The ADC of claim 1 wherein the decoder is connected to the quantizer digital output, wherein the first switch control signal is dependent upon a quantizer digital output value of at least one bit of the quantizer digital output.

6. The ADC of claim 1 wherein a state of the LFSR is advanced at a programmable LFSR clock frequency.

7. The ADC of claim 1 wherein the ADC is selected from a group consisting of a sigma-delta ADC and a pipelined ADC.

8. An analog-to-digital converter (ADC) comprising:
a digital-to-analog converter (DAC), the DAC having a digital input and an analog output; and
a quantizer, the quantizer having a quantizer digital output connected to the digital input, the quantizer comprising:
a random number generator circuit providing a random output;
a decoder connected to the random number generator circuit and configured to provide a plurality of switch control signals at a plurality of decoder outputs, the switch control signals responsive to a random output value of the random output;
an electrical reference having a plurality of reference outputs, each reference output to provide a reference level signal;
a plurality of switches, each switch having an input, a first switch output and a second switch output, the switch input connected to a first one of the decoder outputs to receive a first switch control signals, the first switch output connected to a first one of the reference outputs when the first switch control signal is in a first state and connected to a second one of reference outputs when the first switch control signal is in a second state, and the second switch output connected to the second reference output when the first control signal is in the first state and connected to the first reference output when the first control signal is in the second state, wherein the input of each one of the plurality of switches is connected to a different one of the plurality of decoder outputs; and

a plurality of comparators, each comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output of an associated one of the plurality of switches, and the second reference input connected to the second switch output of the associated switch.

9. The ADC of claim 8 wherein the decoder comprises:
a mode selection input, the mode selection input configured to receive a mode selection value, wherein each decoder output further provides the switch control signal responsive to the mode selection value.

10. The ADC of claim 9 wherein the decoder selects a number of switch control signals to assert based upon the mode selection value.

11. The ADC of claim 9 wherein each switch control signal is asserted based upon an associated bit of the LSFR value when the mode selection value.

12. The ADC of claim 8 wherein the decoder is connected to the quantizer digital output, wherein the first switch control signal is dependent upon a quantizer digital output value of at least one bit of the quantizer digital output.

13. The ADC of claim 8 wherein a state of the random number generator circuit is advanced at a programmable random number generator clock frequency.

14. The ADC of claim 8 wherein the ADC is selected from a group consisting of a sigma-delta ADC and a pipelined ADC.

15. A method of providing an analog-to-digital converter (ADC), the method comprising:
providing, at a linear-feedback shift register (LFSR), an LFSR output;
providing, at a decoder connected to the LFSR output, a plurality of decoder outputs, each decoder output to provide a separate switch control signal responsive to a LFSR value of the LFSR output;
providing a plurality of switches, each switch having a switch input, a first switch output, and a second switch output;
coupling each switch output to an associated one of the decoder outputs to receive one of the separate switch control signals, wherein each decoder output is provided to a different one of the switches;
providing an electrical reference having a plurality of reference outputs, each reference output to provide a reference level signal;
coupling each first switch output to an associated first one of the reference outputs and each second switch output to an associated second one of the reference outputs when the first switch control signal is in a first state;
coupling each first switch output to the associated second reference output and each second switch output to the associated first reference output when the first switch control signal is in a second state;
providing a plurality of comparators, each comparator having a signal input, a first reference input, and a second reference input, wherein each comparator is associate with a different one of the switches;
coupling each first reference input to the first switch output of the associated switch, and each second reference input to the second switch output of the associated switch.

16. The method of claim 15 further comprising:
receiving, by the decoder, a mode selection input, the mode selection input configured to receive a mode selection value, wherein each decoder output further provides the switch control signal responsive to the mode selection value.

17. The method of claim 16 further comprising:
selecting, by the decoder, a number of swit

Assignees

• Nxp Usa Inc

Inventors

• Hales Rex Kenton
• Newman Bruce Michael

Classifications

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/167

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title

• H03M1/0673

  using random selection of the elements (with data-controlled random generator H03M1/0665) · CPC title