Digital to analog converter device

Patent metadata

Field	Value
Publication number	US-10587280-B2
Application number	US-201816211415-A
Country	US
Kind code	B2
Filing date	Dec 6, 2018
Priority date	Dec 29, 2017
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

A digital-to-analog converter (DAC) device includes a DAC circuitry, a calibration circuitry, and a randomization circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to least significant bits of an input signal. The second DAC circuit is configured to output a second signal. The calibration circuitry is configured to compare the first signal with the second signal, in order to calibrate the second DAC circuit. The randomization circuitry is configured to randomize most significant bits of the input signal, in order to generate first control signals, in which the second DAC circuit is further configured to generate the second signal according to the most significant bits or the first control signals.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) device, comprising:
a DAC circuitry, comprising:
a first DAC circuit configured to generate a first signal according to a plurality of least significant bits of an input signal; and
a second DAC circuit configured to output a second signal;
a calibration circuitry configured to compare the first signal with the second signal, in order to calibrate the second DAC circuit; and
a randomization circuitry configured to randomize a plurality of most significant bits of the input signal, in order to generate a plurality of first control signals, wherein the second DAC circuit is further configured to selectively receive the plurality of most significant bits or the plurality of first control signals based on an operation mode of the DAC device to generate the second signal according to the plurality of most significant bits or the plurality of first control signals.

2. The DAC device of claim 1 , wherein each of the first DAC circuit and the second DAC circuit is implemented with a current-steering DAC circuit.

3. The DAC device of claim 1 , wherein the calibration circuitry comprises:
a detector circuit configured to compare the first signal with the second signal, in order to generate a detection signal;
a digital controller circuit configured to perform a calibration operation according to the detection signal, in order to generate a calibration signal; and
a third DAC circuit configured to output a compensation signal according to the calibration signal, in order to calibrate the second DAC circuit.

4. The DAC device of claim 3 , wherein the compensation signal is configured to be summed up with the second signal directly.

5. The DAC device of claim 3 , wherein the compensation signal is inputted to the second DAC circuit directly.

6. The DAC device of claim 3 , further comprising:
a multiplexer circuitry configured to selectively output one of a data signal or a testing signal as the input signal according to a first mode control signal,
wherein the digital controller circuit is further configured to provide the testing signal to the multiplexer circuitry.

7. The DAC device of claim 6 , further comprising:
a first switch configured to be conducted according to the first mode control signal, in order to transmit the plurality of most significant bits of the input signal from the multiplexer circuitry to the second DAC circuit; and
a second switch configured to be conducted according to a second mode control signal, in order to transmit the plurality of most significant bits of the input signal from the multiplexer circuitry to the randomization circuitry, wherein the second mode control signal is an inverse of the first mode control signal.

8. The DAC device of claim 6 , further comprising:
a plurality of switches coupled to a plurality of output terminals of the DAC circuitry, the plurality of switches configured to be conducted according to a second mode control signal to transmit the first signal and the second signal, wherein the second mode control signal is an inverse of the first mode control signal; and
a plurality of resistors coupled to the plurality of switches, the plurality of resistors configured to generate an analog output according to the first signal and the second signal when the plurality of switches are conducted.

9. The DAC device of claim 1 , wherein the randomization circuitry comprises:
a barrel shifter configured to shift the plurality of most significant bits according to a plurality of second control signals;
a mapping circuit configured to output a plurality of shifted signals according to the plurality of shifted partial most significant bits;
a first register configured to output the plurality of shifted signals as the plurality of first control signals according to a clock signal; and
a control circuit configured to generate the plurality of second control signals according to the plurality of most significant bits.

10. The DAC device of claim 9 , wherein the control circuit comprises:
an encoder configured to encode the plurality of most significant bits, in order to generate a third signal;
an adder configured to sum up the third signal and the plurality of second control signals, in order to generate a fourth signal; and
a second register configured to output the plurality of second control signals according to the fourth signal and the clock signal.

11. The DAC device of claim 1 , wherein the randomization circuitry comprises:
a mapping circuit configured to output a plurality of digital codes according to the plurality of most significant bits;
a barrel shifter configured to shift the plurality of digital codes according to a plurality of second control signals;
a first register configured to output the plurality of shifted digital codes as the plurality of first control signals according to a clock signal; and
a control circuit configured to generate the plurality of second control signals according to the plurality of most significant bits.

12. The DAC device of claim 1 , wherein the randomization circuitry comprises:
a pointer configured to perform a calculation according to the plurality of most significant bits, in order to generate a plurality of selection signals;
an encoder configured to generate a plurality of input patterns according to the plurality of most significant bits;
a plurality of multiplexer circuits configured to generate a plurality of shifted signals according to the plurality of selection signals and the plurality of input patterns; and
a register configured to output the plurality of shifted signals as the plurality of first control signals respectively according to a clock signal.

13. The DAC device of claim 1 , wherein the second DAC circuit is configured to convert the plurality of first control signals to the second signal in a first mode, and is configured to convert the plurality of most significant bits to the second signal in a second mode.

14. The DAC device of claim 13 , wherein the calibration circuitry is further configured to perform a calibration operation in the first mode, in order to calibrate the second DAC circuit.

15. The DAC device of claim 1 , wherein the randomization circuitry is configured to randomize the plurality of most significant bits after the second DAC circuit is calibrated, in order to generate the plurality of first control signals.

16. A digital-to-analog converter (DAC) device, comprising:
a DAC circuitry, comprising:
a first DAC circuit configured to generate a first signal according to a plurality of least significant bits of an input signal; and
a second DAC circuit configured to output a second signal;
a calibration circuitry configured to compare the first signal with the second signal, in order to calibrate the second DAC circuit; and
a randomization circuitry configured to randomize a plurality of most significant bits of the input signal, in order to generate a plurality of first control signals, wherein the second DAC circuit is further configured to generate the second signal according to the plurality of most significant bits or the plurality of first control signals, wherein the randomization circuitry comprises:
a mapping circuit configured to output a plurality of digital codes according to the plurality of most significant bits;
a barrel shifter configured to shift the plurality of digital codes according to a plurality of second control signals;
a first register configured to output the plurality of shifted digital codes as the plurality of first control signals according to a

Assignees

• Realtek Semiconductor Corp

Inventors

• Chen Chih-Lung
• Huang Shih-Hsiung

Classifications

• H03M1/0665

  using data dependent selection of the elements, e.g. data weighted averaging · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/68 Primary

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title