Arrays of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stacks

Patent metadata

Field	Value
Publication number	US-10586807-B2
Application number	US-201916437781-A
Country	US
Kind code	B2
Filing date	Jun 11, 2019
Priority date	May 30, 2018
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

First claim

The invention claimed is:

1. An array of elevationally-extending strings of memory cells, comprising:
a vertical stack of alternating insulative tiers and wordline tiers, the wordline tiers having terminal ends corresponding to control-gate regions of individual memory cells, the control-gate regions individually comprising part of a wordline in individual of the wordline tiers;
a charge-blocking region of the individual memory cells extending elevationally along the individual control-gate regions;
charge-storage material of the individual memory cells extending elevationally along individual of the charge-blocking regions;
channel material extending elevationally along the vertical stack;
insulative charge-passage material laterally between the channel material and the charge-storage material; and
elevationally-extending walls laterally separating immediately-laterally-adjacent of the wordlines, the walls comprising laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material, the silicon-containing material comprising at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy.

2. The array of claim 1 wherein the insulative material predominately comprises SiO2.

3. The array of claim 1 wherein the insulative material comprises at least one of silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide.

4. The array of claim 1 wherein the insulative material is ferroelectric.

5. The array of claim 1 wherein the silicon-containing material comprises at least 40 atomic percent of the at least one of elemental-form silicon or a silicon-containing alloy.

6. The array of claim 1 wherein the silicon-containing material predominately comprises undoped elemental-form silicon.

7. The array of claim 1 wherein the silicon-containing material predominately comprises doped elemental-form silicon.

8. The array of claim 1 wherein the silicon-containing material comprises polycrystalline elemental-form silicon.

9. The array of claim 1 wherein the silicon-containing material comprises amorphous elemental-form silicon.

10. The array of claim 1 wherein the silicon-containing material comprises a silicon-containing alloy.

11. An array of elevationally-extending strings of memory cells, comprising:
control circuitry that controls read and write access to the elevationally-extending strings of memory cells;
a vertical stack of alternating insulative tiers and wordline tiers directly above the control circuitry, the wordline tiers having terminal ends corresponding to control-gate regions of individual memory cells, the control-gate regions individually comprising part of a wordline in individual of the wordline tiers;
a charge-blocking region of the individual memory cells extending elevationally along the individual control-gate regions;
charge-storage material of the individual memory cells extending elevationally along individual of the charge-blocking regions;
channel material extending elevationally along the vertical stack;
insulative charge-passage material laterally between the channel material and the charge-storage material; and
elevationally-extending walls laterally separating immediately-laterally-adjacent of the wordlines, the walls comprising laterally-outer insulative material and polysilicon spanning laterally between the laterally-outer insulative material.

12. The array of claim 11 wherein the insulative material predominately comprises SiO2.

13. The array of claim 11 wherein the insulative material comprises at least one of silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide.

14. The array of claim 11 wherein the insulative material is ferroelectric.

Assignees

• Micron Technology Inc

Inventors

• Xie Zhiqiang
• Carlson Chris M
• Dorhout Justin B
• Khandekar Anish A
• Light Greg
• Meyer Ryan
• Parekh Kunal R
• Pavlopoulos Dimitrios
• Shrotri Kunal

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title