Adaptive thermal overshoot and current limiting protection for MOSFETs

Patent metadata

Field	Value
Publication number	US-10586791-B2
Application number	US-201816035007-A
Country	US
Kind code	B2
Filing date	Jul 13, 2018
Priority date	Mar 8, 2018
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

First claim

What is claimed is:

1. An apparatus, comprising:
a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal;
an enable terminal coupled to the first gate terminal for receiving an enable signal;
a first resistor having an first terminal and having a second terminal coupled to the output terminal;
a first current mirror coupled between the first input terminal and the first terminal of the first resistor, and having an input coupled to the first gate terminal; and
a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first resistor;
a second resistor having a first terminal, and having a second terminal coupled to a ground terminal;
a first current source coupled between the first input terminal and the first terminal of the second resistor;
a third resistor having a first terminal, and having a second terminal coupled to the ground terminal;
a second current mirror coupled between the first input terminal and the first terminal of the third resistor, the second current mirror having an input coupled to the first gate terminal;
a third MOSFET coupled between the first gate terminal and the ground terminal, and having a third gate terminal;
a first comparator having a first input coupled to the first terminal of the second resistor, having a second input coupled to the first terminal of the third resistor, and having an output coupled to the third gate terminal of the third MOSFET.

2. The apparatus of claim 1 , including:
a first thermal sensor coupled to sense a temperature of the first MOSFET and having an output; and
a second comparator having a first input coupled to a voltage at a node corresponding to a limit temperature and having a second input coupled to the output of the first thermal sensor, and having an output coupled to the first gate terminal.

3. The apparatus of claim 2 , in which the first comparator is a hysteresis comparator.

4. The apparatus of claim 3 , in which the first thermal sensor includes:
a second current source coupled between a positive power supply terminal and a first diode connected bipolar transistor; and
a fourth series resistor having a first terminal coupled to the first diode connected bipolar transistor and having a second terminal coupled to the ground terminal.

5. The apparatus of claim 4 , including:
a third comparator having a first input coupled to an ambient thermal sensor and having a second input coupled to the first thermal sensor, and having an output coupled to the first gate terminal.

6. The apparatus of claim 5 , in which the ambient thermal sensor further includes a third current source coupled to the positive power supply terminal and to a first terminal of a second diode connected bipolar transistor having a second terminal coupled to the ground terminal.

7. The apparatus of claim 6 in which the second comparator is a hysteresis comparator.

8. The apparatus of claim 7 , including a first logic gate coupled to the output of the first comparator and to the output of the second comparator, and having an output coupled to a first input of a second logic gate that has a second input coupled to the enable terminal, in which the second logic gate has an output coupled to the first gate terminal.

9. The apparatus of claim 8 in which the first logic gate is an OR gate.

10. The apparatus of claim 9 including an inverter between the output of the first logic gate and the input of the second logic gate.

11. The apparatus of claim 10 in which the second logic gate is an AND gate.

12. The apparatus of claim 1 in which the first MOSFET is a power MOSFET that has a first width to length (W/L) ratio that is at least 100 times greater than a second W/L ratio of the second MOSFET.

13. The apparatus of claim 1 in which the first current mirror includes a fifth MOSFET having a gate coupled to the first gate terminal, a drain coupled to the first terminal and a source coupled to the first series resistor.

14. The apparatus of claim 1 in which the first MOSFET is an n-type enhancement mode MOSFET.

15. An integrated circuit, comprising:
a supply terminal;
a load terminal;
an enable terminal;
a ground terminal;
a first metal-oxide-semiconductor field-effect-transistor (MOSFET) coupled between the supply terminal and the load terminal and having a first gate terminal coupled to the enable terminal;
a first resistor having a first terminal, and having a second terminal coupled to the load terminal;
a second MOSFET having a second gate terminal coupled to the first gate terminal, the second MOSFET coupled between the supply terminal and the first terminal of the first resistor; and
a third MOSFET coupled between the first gate terminal and the load terminal and having a gate terminal coupled to the first terminal of the first resistor;
a second resistor having a first terminal and having a second terminal coupled to the ground terminal;
a first current mirror coupled between the supply terminal and the first terminal of the second resistor;
a third resistor having a first terminal, and having a second terminal coupled to the ground terminal;
a first current source coupled to the supply terminal and having an output coupled to the first terminal of the third resistor;
an operational amplifier having a first input coupled to the second resistor and a second input coupled to the third resistor and having an output; and
a fourth MOSFET coupled between the first gate terminal and the ground terminal and having a third gate terminal coupled to the output of the operational amplifier.

16. The integrated circuit of claim 15 including:
a first thermal sensor coupled to sense a temperature of the first MOSFET;
a first switch coupled to select between a voltage corresponding to a first thermal limit and a second thermal limit less than the first thermal limit, and having a switch output; and
a first hysteresis comparator having a first input coupled to the first thermal sensor and a second input coupled to the switch output, and having an output coupled to the first gate terminal.

17. The integrated circuit of claim 16 , including:
a second thermal sensor coupled to sense the temperature of the integrated circuit at a position spaced from the first MOSFET; and
a second hysteresis comparator having a first input coupled to the first thermal sensor, a second input coupled to the second thermal sensor, and an output coupled to the first gate terminal.

18. The integrated circuit of claim 15 , in which the first MOSFET is a power MOSFET device that is an n-type enhancement node MOSFET transistor.

19. The integrated circuit of claim 15 , in which the first MOSFET has a width over length (W/L) ratio that is greater than 100 times a W/L ratio of the second MOSFET.

20. The integrated circuit of claim 15 including an additional MOSFET coupled between the first terminal for receiving the voltage supply and to an additional output terminal for coupling to an additional load, and having a gate terminal coupled to an additional enable signal.

Assignees

• Texas Instruments Inc

Inventors

• Ma Qingjie
• Xu Wei
• Xu Jingwei
• Wang Yang

Classifications

• H03K2017/0806

  against excessive temperature · CPC title

• H03K17/08104 Primary

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K17/08122

  in field-effect transistor switches · CPC title

• H01L27/0277 Primary

  Electricity · mapped topic

• H10D89/811

  using FETs as protective elements · CPC title