Method for manufacturing pairs of CMOS transistors of the “fin-FET” type at low temperatures

Patent metadata

Field	Value
Publication number	US-10586740-B2
Application number	US-201816191951-A
Country	US
Kind code	B2
Filing date	Nov 15, 2018
Priority date	Nov 23, 2017
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

Method for producing a device provided with FinFET transistors, comprising the following steps:
a) making amorphous and doping a first portion of a semiconductor in via a tilted beam oriented toward a first lateral face of the fin, while retaining a first crystalline semiconductor block against a second lateral face of the fin, then b) carrying out at least one recrystallization annealing of said first portion, then c) making amorphous and doping a second portion via a tilted beam oriented toward the second lateral face of the fin, while retaining a second crystalline semiconductor block against said first lateral face of the fin, then d) carrying out at least one recrystallization annealing of the second portion.

First claim

The invention claimed is:

1. A method for producing a device provided with one or several FinFET transistor(s) comprising the following steps:
a) making amorphous and doping a first portion of at least one semiconductor structure comprising a fin made from a crystalline semiconductor material and extending over a substrate in the direction of its length in a first direction Y, the fin having a height measured in a second direction Z orthogonal to the first direction, the first direction Y and the second direction Z being parallel to a longitudinal plane P 1 normal to the primary plane of the substrate, the first portion being made amorphous and doped using at least a first tilted implantation via a beam oriented toward a first lateral face of the fin and along a direction forming a non-nil angle −θ 1 with the second direction Z, the direction of the beam being located in a transverse plane, the transverse plane being normal to the primary plane of the support and secant, or advantageously orthogonal, to the longitudinal plane, the first portion made amorphous and doped being arranged against the first lateral face and extending up to a given zone of the fin located between the first lateral face and a second lateral face opposite the first lateral face, a first crystalline semiconductor block being kept against the second lateral face of the fin, then
b) carrying out at least one recrystallization annealing of said first portion, then
c) making amorphous and doping a second portion of the fin using a beam oriented toward the second lateral face of the fin and along a direction forming a non-nil angle +θ 2 with the second direction Z, the second portion made amorphous and doped being arranged against the second lateral face and extending up to a given part of the fin located between the first lateral face and the second lateral face, a second crystalline semiconductor block being kept against the first lateral face of the fin, then
d) carrying out at least one recrystallization annealing of the second portion.

2. The method according to claim 1 , wherein during the first implantation and the second implantation, the fin may be covered by a transistor gate pattern.

3. The method according to claim 1 , wherein the semiconductor structure comprises another fin, adjacent to said fin, the method further comprising, before the first implantation, forming an implantation mask on said other fin.

4. The method according to claim 1 , wherein during the first implantation and the second implantation, an upper face of said fin is covered with a mask element.

5. The method according to claim 1 , wherein the recrystallization annealing of the first portion and/or the recrystallization annealing of the second portion is done at a temperature below 600° C.

6. The method according to claim 1 , wherein the device is a 3D circuit provided with levels of superimposed transistors, the FinFET transistor(s) being transistors of a given level of transistor(s) and the substrate including at least one level of transistors below the given level and having a channel region arranged in a first semiconductor layer, the first semiconductor layer being covered with at least one intermediate insulating layer between the fin made from crystalline semiconductor material and the first semiconductor layer.

7. The method according to claim 2 , the method further comprising, after the annealing of the second portion, the formation of insulating spacers on either side of the gate pattern.

8. The method according to claim 7 , the method further comprising, after formation of the insulating spacers, steps for:
etching first volumes of the fin on either side of the insulating spacers, then
forming semiconductor regions to replace said first volumes by growth of a semiconductor material that is doped and/or that has a mesh parameter different from the mesh parameter of said crystalline semiconductor material.

9. The method according to claim 7 , wherein the gate pattern is that of a sacrificial gate, the method further comprising, after formation of the insulating spacers, steps for:
removing the sacrificial gate pattern,
forming a replacement gate between the spacers.

10. The method according to claim 3 , wherein the production of the implantation mask comprises the following steps:
forming a mask layer covering an upper face and lateral faces of the fin,
selectively removing the mask layer on the lateral faces of said fin while preserving the mask layer on said other fin.

11. The method according to claim 3 , wherein the implantation mask is made from silicon nitride.

12. The method according to claim 10 , wherein the deposition of the mask layer is done such that the mask layer has a greater thickness in a zone located on an upper face of the fins than in a zone located against the lateral faces of the fins.

13. The method according to claim 10 , wherein the mask layer is a layer of silicon nitride, the method further comprising the following steps:
selective oxidation of a portion of the silicon nitride layer located across from said other fin, while protecting another portion of the silicon nitride layer located across from said fin,
selective etching of said other portion of the nitride layer across from the oxidized portion of the silicon nitride layer.

Assignees

• Commissariat Energie Atomique

Inventors

• Mathieu Benoit
• Batude Perrine

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P30/22

  using masks · CPC title

• H01L21/0337

  Electricity · mapped topic

• H01L21/823864

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic