Semiconductor base having a composition graded buffer layer stack

Patent metadata

Field	Value
Publication number	US-10586701-B2
Application number	US-201616077263-A
Country	US
Kind code	B2
Filing date	Feb 26, 2016
Priority date	Feb 26, 2016
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

Semiconductor base including: silicon-based substrate; buffer layer including first and second layers alternately on silicon-based substrate, first layer made of nitride-based compound semiconductor containing first material, second layer made of nitride-based compound semiconductor containing second material having larger lattice constant than first material; channel layer on buffer layer and made of nitride-based compound semiconductor containing second material, buffer layer has: first composition graded layer between at least one of first layers and second layer immediately thereabove, made of nitride-based compound semiconductor whose composition ratio of second material is increased gradually upward, whose composition ratio of first material is decreased gradually upward; second composition graded layer between at least one of second layers and first layer immediately thereabove, made of nitride-based compound semiconductor whose first material is increased gradually upward, whose composition ratio of second material is decreased gradually upward, first composition graded layer is thicker than second composition graded layer.

First claim

The invention claimed is:

1. A semiconductor base comprising:
a silicon-based substrate;
a buffer layer comprising layers including first layers and second layers alternately provided on the silicon-based substrate, the first layers being made of a nitride-based compound semiconductor containing a first material, and the second layers being made of a nitride-based compound semiconductor containing a second material having a larger lattice constant than the first material; and
a channel layer provided on the buffer layer and made of a nitride-based compound semiconductor containing the second material,
wherein the buffer layer further comprises:
a first composition graded layer which is provided between at least one of the first layers and the second layer immediately thereabove, and which is made of a nitride-based compound semiconductor whose composition ratio of the second material is increased gradually upward and whose composition ratio of the first material is decreased gradually upward; and
a second composition graded layer which is provided between at least one of the second layers and the first layer immediately thereabove, and which is made of a nitride-based compound semiconductor whose composition ratio of the first material is increased gradually upward and whose composition ratio of the second material is decreased gradually upward, and
the first composition graded layer is thicker than the second composition graded layer.

2. The semiconductor base according to claim 1 , wherein average of composition rates of change in relation to a thickness of the first composition graded layer are smaller than average of composition rates of change in relation to a thickness of the second composition graded layer.

3. The semiconductor base according to claim 1 , wherein the first composition graded layer is present between every pair of the first layer and the second layer immediately thereabove, and
the second composition graded layer is present between every pair of the second layer and the first layer immediately thereabove.

4. The semiconductor base according to claim 2 , wherein
the first composition graded layer is present between every pair of the first layer and the second layer immediately thereabove, and
the second composition graded layer is present between every pair of the second layer and the first layer immediately thereabove.

5. The semiconductor base according to claim 1 , wherein
the first composition graded layer is provided as an uppermost layer in the buffer layer, and
the first layer is provided under the first composition graded layer.

6. The semiconductor base according to claim 2 , wherein
the first composition graded layer is provided as an uppermost layer in the buffer layer, and
the first layer is provided under the first composition graded layer.

7. The semiconductor base according to claim 3 , wherein
the first composition graded layer is provided as an uppermost layer in the buffer layer, and
the first layer is provided under the first composition graded layer.

8. The semiconductor base according to claim 1 , wherein
the first material and the second material are selected from the group consisting of B, Al, Ga, and In.

9. The semiconductor base according to claim 2 , wherein
the first material and the second material are selected from the group consisting of B, Al, Ga, and In.

10. The semiconductor base according to claim 3 , wherein
the first material and the second material are selected from the group consisting of B, Al, Ga, and In.

11. The semiconductor base according to claim 1 , wherein
the first layer is an AlN layer, and
the second layer is a GaN layer.

12. The semiconductor base according to claim 2 , wherein
the first layer is an AlN layer, and
the second layer is a GaN layer.

13. The semiconductor base according to claim 3 , wherein
the first layer is an AlN layer, and
the second layer is a GaN layer.

14. The semiconductor base according to claim 11 , wherein an average of composition rates of change of the first material in the first and second composition graded layers is larger than 29%/nm but not larger than 75%/nm.

15. The semiconductor base according to claim 12 , wherein an average of composition rates of change of the first material in the first and second composition graded layers is larger than 29%/nm but not larger than 75%/nm.

16. The semiconductor base according to claim 13 , wherein an average of composition rates of change of the first material in the first and second composition graded layers is larger than 29%/nm but not larger than 75%/nm.

17. A semiconductor device comprising an electrode on the semiconductor base according to claim 1 .

18. A semiconductor device comprising an electrode on the semiconductor base according to claim 2 .

19. A semiconductor device comprising an electrode on the semiconductor base according to claim 3 .

Assignees

• Sanken Electric Co Ltd
• Shinetsu Handotai Kk

Inventors

• Shikauchi Hiroshi
• Sato Ken
• Shinomiya Masaru
• Tsuchiya Keitaro
• Hagimoto Kazunori

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3254 Primary

  Graded layers · CPC title