Shift register, gate driving circuit, display device, and driving method thereof

Patent metadata

Field	Value
Publication number	US-10586604-B1
Application number	US-201816230484-A
Country	US
Kind code	B1
Filing date	Dec 21, 2018
Priority date	Aug 30, 2018
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register.

First claim

What is claimed is:

1. A shift register, comprising:
a forward/backward (FW/BW) scan-control module, configured to, in response to a signal of a first control terminal, transmit a signal of a forward-scan-signal terminal to a first node, and in response to a signal of a second control terminal, transmit a signal of a backward-scan-signal terminal to the first node;
an interlock module, configured to, in response to a signal of the first node, transmit a signal of a first voltage terminal to a second node, and in response to a signal of the second node, transmit a signal of a second voltage terminal to the first node;
a pull-down module, configured to, in response to a signal of a first clock-signal terminal, transmit the signal of the first voltage terminal to a gate-signal output terminal;
an output module, configured to, in response to the signal of the first node, transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and
a reset module, configured to, in response to a signal of a third control terminal, transmit the signal of the second voltage terminal to the first node, and in response to a signal of a fourth control terminal, transmit the signal of the first voltage terminal to the gate-signal output terminal.

2. The shift register according to claim 1 , wherein:
the FW/BW scan-control module includes a zeroth transistor and a first transistor, wherein:
a gate of the zeroth transistor is electrically connected to the first control terminal, a first terminal of the zeroth transistor is electrically connected to the forward-scan-signal terminal, and a second terminal of the zeroth transistor is electrically connected to the first node, and
a gate of the first transistor is electrically connected to the second control terminal, a second terminal of the first transistor is electrically connected to the backward-scan-signal terminal, and a first terminal of the first transistor is electrically connected to the first node.

3. The shift register according to claim 1 , wherein:
the interlock module includes a second transistor, a third transistor, and a second capacitor, wherein:
a gate of the second transistor is electrically connected to the second node, a second terminal of the second transistor is electrically connected to the second voltage terminal, and a first terminal of the second transistor is electrically connected to the first node,
a gate of the third transistor is electrically connected to the first node, a second terminal of the third transistor is electrically connected to the first voltage terminal, and a first terminal of the third transistor is electrically connected to the second node, and
a second electrode plate of the second capacitor is electrically connected to the second node, and a first electrode plate of the second capacitor is electrically connected to the second clock-signal terminal.

4. The shift register according to claim 1 , wherein:
the output module includes a fourth transistor and a first capacitor, wherein:
a gate of the fourth transistor is electrically connected to the first node, a first terminal of the fourth transistor is electrically connected to the second clock-signal terminal, and a second terminal of the fourth transistor is electrically connected to the gate-signal output terminal, and
a first electrode plate of the first capacitor is electrically connected to the first node, and a second electrode plate of the first capacitor is electrically connected to the gate-signal output terminal.

5. The shift register according to claim 1 , wherein:
the pull-down module includes a sixth transistor, wherein:
a gate of the sixth transistor is electrically connected to the first clock-signal terminal, a second terminal of the sixth transistor is electrically connected to the first voltage terminal, and a first terminal of the sixth transistor is electrically connected to the gate-signal output terminal.

6. The shift register according to claim 5 , wherein:
the pull-down module further includes a fifth transistor, wherein:
a gate of the fifth transistor is electrically connected to the second node, a second terminal of the fifth transistor is electrically connected to the first voltage terminal, and a first terminal of the fifth transistor is electrically connected to the gate-signal output terminal.

7. The shift register according to claim 1 , wherein:
the reset module includes a seventh transistor and an eighth transistor, wherein:
a gate of the seventh transistor is electrically connected to the fourth control terminal, a second terminal of the seventh transistor is electrically connected to the first voltage terminal, and a first terminal of the seventh transistor is electrically connected to the gate-signal output terminal, and
a gate of the eighth transistor is electrically connected to the third control terminal, a second terminal of the eighth transistor is electrically connected to the second voltage terminal, and a first terminal of the eighth transistor is electrically connected to the first node.

8. The shift register according to claim 7 , wherein:
the third control terminal is electrically connected to a first reset-signal terminal; and
the fourth control terminal is electrically connected to a second reset-signal terminal.

9. The shift register according to claim 7 , wherein:
the third control terminal and the fourth control terminal are both electrically connected to a reset-signal terminal.

10. The shift register according to claim 1 , wherein:
the forward-scan-signal terminal is electrically connected to the first control terminal.

11. A gate driving circuit, comprising X cascaded shift registers, where X is an integer greater than or equal to 3, wherein:
each shift register of the X cascaded shift registers includes a FW/BW scan-control module, an interlock module, a pull-down module, an output module, and a reset module, wherein:
the FW/BW scan-control module is configured to, in response to a signal of a first control terminal, transmit a signal of a forward-scan-signal terminal to a first node, and in response to a signal of a second control terminal, transmit a signal of a backward-scan-signal terminal to the first node,
the interlock module is configured to, in response to a signal of the first node, transmit a signal of a first voltage terminal to a second node, and in response to a signal of the second node, transmit a signal of a second voltage terminal to the first node,
the pull-down module is configured to, in response to a signal of a first clock-signal terminal, transmit the signal of the first voltage terminal to a gate-signal output terminal,
the output module is configured to, in response to the signal of the first node, transmit a signal of a second clock-signal terminal to the gate-signal output terminal, and
the reset module is configured to, in response to a signal of a third control terminal, transmit the signal of the second voltage terminal to the first node, and in response to a signal of a fourth control terminal, transmit the signal of the first voltage terminal to the gate-signal output terminal.

12. The gate driving circuit according to claim 11 , wherein:
for an (x)th shift register, where x is a positive integer and 2≤x≤(X−1), a first control terminal of the (x)th shift register is electrically connected to a gate-signal output terminal of an (x−1)th shift register, and a second control terminal of the (x)th shift register is electrically connected to a gate-signal output terminal of an (x+1)th shift register.

13. The gate driving circuit according to claim 11 , wherein:
in the each shift

Assignees

• Shanghai Avic Opto Electronics Co Ltd

Inventors

• Fei Rili
• Xia Zhiqiang
• Qin Dandan
• Dun Dongliang
• Jian Shoufu
• Wang Tinghai
• Xie Ying
• Xia Houxun

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0281

  Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title