Machine learning document processing
US-2019065991-A1 · Feb 28, 2019 · US
US10586001B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10586001-B2 |
| Application number | US-201916242746-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 8, 2019 |
| Priority date | Jan 8, 2018 |
| Publication date | Mar 10, 2020 |
| Grant date | Mar 10, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug field, yielding possible values for a subset of debug fields. A clone violation may be created for a combination of the at least two second debug fields, populating a projection matrix, which may be used to map violations and clone violations to corresponding numerical values in the projection matrix and determine a violation cluster based on the mapping having corresponding numerical values and score(s) satisfying a threshold, via ML. Clustering may further be used to generate visualizations.
Opening claim text (preview).
We claim: 1. A system for performing automated root-cause analysis, comprising: memory and at least one computer processor communicatively coupled with the memory and configured to: receive a report comprising a plurality of violations and a plurality of debug fields; accept a selection of a seed debug field from among the plurality of debug fields; generate a plurality of clone violations, wherein to generate the plurality of clone violations, the at least one computer processor is further configured to: calculate, via an overlay mechanism, an overlay of a given violation of the plurality of violations and the seed debug field, wherein the overlay mechanism yields a plurality of possible values for a subset of the plurality of debug fields; and create a given clone violation for a given combination of at least two second debug fields; populate a projection matrix; produce a mapping of the plurality of violations and the plurality of clone violations to corresponding numerical values in the projection matrix; and determine a violation cluster based on the mapping having a set of corresponding numerical values having one or more scores satisfying at least one score threshold, via a machine-learning algorithm. 2. The system of claim 1 , wherein the one or more scores comprise a structural cohesion index. 3. The system of claim 1 , wherein the one or more scores comprise a quality score. 4. The system of claim 1 , wherein the machine-learning algorithm comprises a mean-shift algorithm, k-means clustering, balanced iterative reducing and clustering using hierarchies (BIRCH), or a combination thereof. 5. The system of claim 1 , wherein the plurality of violations comprises a Unified Power Format (UPF) violation. 6. The system of claim 1 , wherein the report is generated by a debugging tool. 7. The system of claim 6 , wherein the debugging tool comprises an electronic design automation (EDA) tool, a circuit simulator, a clock-domain crossing (CDC) checker, a static verification tool, or a combination thereof. 8. A method of automated root-cause analysis, comprising: receiving, by at least one computer processor, a report comprising a plurality of violations and a plurality of debug fields; accepting, by the at least one computer processor, a selection of a seed debug field from among the plurality of debug fields; generating, by the at least one computer processor, a plurality of clone violations, wherein the generating comprises: calculating, by the at least one computer processor, via an overlay mechanism, an overlay of a given violation of the plurality of violations and the seed debug field, wherein the overlay mechanism yields a plurality of possible values for a subset of the plurality of debug fields; and creating, by the at least one computer processor, a given clone violation for a given combination of at least two second debug fields; populating, by the at least one computer processor, a projection matrix; producing, by the at least one computer processor, a mapping of the plurality of violations and the plurality of clone violations to corresponding numerical values in the projection matrix; and determining, by the at least one computer processor, a violation cluster based on the mapping having a set of corresponding numerical values having one or more scores satisfying at least one score threshold, via a machine-learning algorithm. 9. The method of claim 8 , wherein the one or more scores comprise a structural cohesion index. 10. The method of claim 8 , wherein the one or more scores comprise a quality score. 11. The method of claim 8 , wherein the machine-learning algorithm comprises a mean-shift algorithm, k-means clustering, balanced iterative reducing and clustering using hierarchies (BIRCH), or a combination thereof. 12. The method of claim 8 , wherein the plurality of violations comprises a Unified Power Format (UPF) violation. 13. The method of claim 8 , wherein the report is generated by a debugging tool. 14. The method of claim 13 , wherein the debugging tool comprises an electronic design automation (EDA) tool, a circuit simulator, a clock-domain crossing (CDC) checker, a static verification tool, or a combination thereof. 15. A non-transitory computer-readable storage device having instructions stored thereon, wherein the instructions, when executed, cause at least one computer processor to perform operations for automated root-cause analysis, the operations comprising: receiving a report comprising a plurality of violations and a plurality of debug fields; accepting a selection of a seed debug field from among the plurality of debug fields; generating a plurality of clone violations, wherein the generating comprises: calculating via an overlay mechanism, an overlay of a given violation of the plurality of violations and the seed debug field, wherein the overlay mechanism yields a plurality of possible values for a subset of the plurality of debug fields; and creating a given clone violation for a given combination of at least two second debug fields; populating a projection matrix; producing a mapping of the plurality of violations and the plurality of clone violations to corresponding numerical values in the projection matrix; and determining a violation cluster based on the mapping having a set of corresponding numerical values having one or more scores satisfying at least one score threshold, via a machine-learning algorithm. 16. The non-transitory computer-readable storage device of claim 15 , wherein the one or more scores comprise a structural cohesion index. 17. The non-transitory computer-readable storage device of claim 15 , wherein the one or more scores comprise a quality score. 18. The non-transitory computer-readable storage device of claim 15 , wherein the machine-learning algorithm comprises a mean-shift algorithm, k-means clustering, balanced iterative reducing and clustering using hierarchies (BIRCH), or a combination thereof. 19. The non-transitory computer-readable storage device of claim 15 , wherein the plurality of violations comprises a Unified Power Format (UPF) violation. 20. The non-transitory computer-readable storage device of claim 15 , wherein the report is generated by a debugging tool, and wherein the debugging tool comprises an electronic design automation (EDA) tool, a circuit simulator, a clock-domain crossing (CDC) checker, a static verification tool, or a combination thereof.
using formal methods, e.g. equivalence checking or property checking · CPC title
Machine learning · CPC title
Physics · mapped topic
Physics · mapped topic
Drawing of charts or graphs · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.