Power supply diagnostic strategy

Patent metadata

Field	Value
Publication number	US-10585772-B2
Application number	US-201414447595-A
Country	US
Kind code	B2
Filing date	Jul 30, 2014
Priority date	Jun 4, 2013
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

A power supply diagnostic strategy for discrete power supply diagnostic states is independent of the underlying memory structure. The values used in the associated algorithm are selected to ensure that random linked failures will be detected. This applies to planar memory structures with 1, 2, 4, 6, 8, 12, and 16 common lattices, or physical memory structures with individual bit dispersed memories with 1, 2, 4, 6, 8, 12, and 16 consecutive bit splices. Further, the strategy provides that the various monitored voltage tables remains distinct even with compiler optimization activated.

First claim

What is claimed is:

1. A method for diagnosing the status of an operating voltage comprising the steps of:
(a) using a regulated voltage power supply to generate an operating voltage;
(b) supplying the operating voltage to an over voltage/under voltage monitor, the monitor generating a first status signal indicating when an over voltage condition exists and a second status signal indicating when an under voltage condition exists;
(c) using a processor to read the first and second status signals and to determine one of the following states: (1) “no” OV, “no” UV; (2) “no” OV, “yes” UV; (3) “yes” OV, “no” UV or (4) “yes” OV, “yes” UV;
(d) assigning a distinct byte value for each of the states identified in step (c), wherein each distinct byte value includes a USNb and a LSNb, and wherein all of the USNbs are distinct and are selected having a hamming distance of at least 2, and all the LSNbs are distinct and are selected having a hamming distance of at least 2, and wherein the distinct values are selected having a hamming distance of at least 4; and
(e) storing an operating status value corresponding to the determined operating state in a designated memory location of the processor.

2. The method of claim 1 wherein each of the USNbs and LSNbs are chosen from an unbalanced set of nibble values.

3. The method of claim 2 wherein each of the USNbs and LSNbs are chosen for each distinct value such that they are not complements of one another.

4. The method of claim 2 wherein the unbalanced set of nibbles include hex values 1, 2, 4, 7, 8, B, D and E.

5. The method of claim 4 wherein the USNbs are selected from the group 7, B, D and E and the LSNbs are selected from the group 1, 2, 4 and 8.

6. The method of claim 5 wherein the distinct values of step (d) include 74, B 2 , D 1 and E 8 .

7. The method of claim 1 wherein, prior to step (e), the distinct byte value is checked for a match with one of a group of defined values and, if there is a match, the distinct byte value is stored as the operating status value and, if there is no match, a separate “no match” value is stored.

8. A method for diagnosing the status of an operating voltage comprising the steps of:
(a) using a regulated voltage power supply to generate an operating voltage;
(b) supplying the operating voltage to an over voltage/under voltage monitor, the monitor generating a first status signal indicating when an over voltage condition exists and a second status signal indicating when an under voltage condition exists;
(c) using a processor to read the first and second status signals and to determine one of the following states: (1) “no” OV, “no” UV; (2) “no” OV, “yes” UV; (3) “yes” OV, “no” UV or (4) “yes” OV, “yes” UV;
(d) assigning a distinct byte value for each of the states identified in step (c), wherein the distinct values are selected having a hamming distance of at least 4 wherein the distinct byte value is a lower byte of a word,
(e) assigning an upper byte value to the word, the upper byte value including a USNb and a LSNb, and wherein one of the USNb and LSNb is a monitored voltage identifier and the other one is a control/diagnostic path identifier; and
(f) storing an operating status value corresponding to the determined operating state in a designated memory location of the processor.

9. The method of claim 8 wherein each of the USNbs and LSNbs of the upper byte are chosen from an balanced set of nibble values.

10. A method for diagnosing the status of an operating voltage comprising the steps of:
(a) using a regulated voltage power supply to generate the operating voltage;
(b) supplying the operating voltage to an over voltage/under voltage monitor, the monitor generating a first status signal indicating when an over voltage condition exists and a second status signal indicating when an under voltage condition exists;
(c) using a processor to read the first and second status signals and to determine one of the following control states: (1) “no” OV, “no” UV; (2) “no” OV, “yes” UV; (3) “yes” OV, “no” UV or (4) “yes” OV, “yes” UV;
(d) assigning a distinct control byte value for each of the control states identified in step (c) wherein each distinct control byte value includes a USNb and a LSNb, and wherein all of the USNbs and LSNbs are distinct;
(e) storing an operating control status value corresponding to the determined operating state in a designated control memory location of the processor;
(f) using the processor of step (c) to read the operating voltage and to determine one of the following diagnostic states: (1) “no” OV, “no” UV; (2) “no” OV, “yes” UV; (3) “yes” OV, “no” UV or (4) “yes” OV, “yes” UV;
(g) assigning a distinct diagnostic byte value for each of the states identified in step (d);
(h) storing an operating diagnostic status value corresponding to the determined operating state in a designated diagnostic memory location of the processor; and
(i) comparing the operating control status value with the operating diagnostic status value to determine whether the control voltage state read in step (c) agrees with the diagnostic voltage state read in step (f).

11. The method of claim 10 wherein each distinct diagnostic byte value of step (h) includes a USNb and a LSNb, and wherein all of the USNbs and LSNbs are distinct.

12. The method of claim 11 wherein the USNb and LSNb of the diagnostic byte value are mirrored with respect to the USNb and LSNb of the corresponding control byte value.

13. The method of claim 12 wherein both the USNb and LSNb of the diagnostic byte value are compared to the mirrored USNb and LSNb of the corresponding control byte value.

14. The method of claim 12 wherein only one of the USNb and LSNb of the diagnostic byte value is compared to one of the mirrored USNb and LSNb of the corresponding control byte value.

15. A method for diagnosing the status of an operating voltage comprising the steps of:
(a) using a regulated voltage power supply to generate the operating voltage;
(b) supplying the operating voltage to an over voltage/under voltage monitor, the monitor generating a first status signal indicating when an over voltage condition exists and a second status signal indicating when an under voltage condition exists;
(c) using a processor to read the first and second status signals and to determine one of the following control states: (1) “no” OV, “no” UV; (2) “no” OV, “yes” UV; (3) “yes” OV, “no” UV or (4) “yes” OV, “yes” UV;
(d) assigning a distinct control byte value for each of the control states identified in step (c);
(e) checking the distinct control byte value for a match with one of a group of defined control values and, if there is a match, storing the distinct control byte value corresponding to the determined operating state in a designated control memory location of the processor as an operating control status value and, if there is no match, storing a separate “no match” control value;
(f) using the processor of step (c) to read the operating voltage and to determine one of the following diagnostic states: (1) “no” OV, “no” UV; (2) “no” OV, “yes” UV; (3) “yes” OV, “no” UV or (4) “yes” OV, “yes” UV;
(g) assigning a distinct diagnostic byte value for each of the states identified in step (d);
(h) storing an operating diagnostic status value corresponding to the determined operating state in a designated diagnostic memory location of the processor; and
(i) comparing the operating control status value with the operating diagnostic status value to determine whether the control voltage state read in step (c) agrees with the diagnostic voltage state read in step (f).

Assignees

• Trw Automotive Us Llc

Inventors

• Katrak Kerfegar K

Classifications

• G06F11/3013

  where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems (testing or monitoring of control systems or parts thereof G05B23/02) · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• H02H1/0092

  concerning the data processing means, e.g. expert systems, neural networks · CPC title

• G06F11/24 Primary

  Marginal checking {or other specified testing methods not covered by G06F11/26, e.g. race tests} · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title