Low power autonomous peripheral management

Patent metadata

Field	Value
Publication number	US-10585448-B2
Application number	US-201715841673-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Oct 20, 2014
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

First claim

What is claim is:

1. An integrated circuit comprising an autonomous peripheral facility, said autonomous peripheral facility comprising:
a central processing unit (CPU) adapted to develop a first input;
a peripheral device adapted to receive a first data input, develop a first data output, and develop a first information data; and
a peripheral controller comprising a configuration register, a state machine, a control unit, and a memory, said peripheral controller being adapted to receive said first input, to exchange said first information data, and to autonomously operate said peripheral device, independent of said CPU after receiving said first input, wherein:
said configuration register is further adapted to receive said first input and develop a first control data as a function of said first input;
said peripheral device is further adapted to exchange said first information data with a selected one of said control unit and a data memory;
said state machine is further adapted to:
selectively receive a trigger; and
perform at least one of:
selectively sequence a plurality of peripheral modes as a function of said first control data and said trigger;
selectively develop a first completion signal as a function of said first control data;
selectively develop a first power switch signal as a function of said first control data; and

selectively develop a plurality of clocks as a function of said first control data and said trigger;

said control unit is further adapted to:
exchange said first information data with said peripheral device, said memory, and said state machine; and
selectively sequence a plurality of peripheral power states as a function of said first control data and said trigger; and

said memory adapted to store said first information data.

2. The autonomous peripheral facility of claim 1 wherein said trigger is further characterized as being a function of said first control data.

Assignees

• Ambiq Micro Inc

Inventors

• Sheafor Stephen James
• Hanson Scott
• Popps Donovan

Classifications

• H03L7/181

  a numerical count result being used for locking the loop, the counter counting during fixed time intervals {(H03L7/1806 takes precedence)} · CPC title

• G06F1/06 Primary

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title