Testing integrated circuit designs containing multiple phase rotators

Patent metadata

Field	Value
Publication number	US-10585140-B2
Application number	US-201715816486-A
Country	US
Kind code	B2
Filing date	Nov 17, 2017
Priority date	Jan 15, 2014
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

First claim

What is claimed is:

1. A method of testing a plurality of phase rotators, comprising:
connecting a first phase source to a first input of a compare element;
connecting a second phase source to a second input of the compare element, wherein the second phase source comprises an output of one of the plurality of phase rotators that are selectively connectable to the second input;
generating an expected value of a phase relationship between the first phase source and the second phase source; and
comparing the expected value to an output of the compare element.

2. The method of claim 1 , wherein the first phase source comprises one of:
an output of another one of the plurality of phase rotators; and
an output of a phase locked loop.

3. The method of claim 1 , further comprising:
selecting at least one of a first phase and a first weight for the first phase source; and
selecting at least one of a second phase and a second weight for the second phase source.

4. The method of claim 1 , further comprising repeating the connecting the second phase source, the generating, and the comparing for each one of the plurality of phase rotators.

5. The method of claim 1 , wherein the compare element comprises a tunable AND gate.

6. The method of claim 5 , further comprising providing a control signal to the tunable AND gate, wherein the control signal provides timing control.

7. The method of claim 5 , further comprising providing a control signal to the tunable AND gate, wherein the control signal provides minimum pulse width control.

8. The method of claim 5 , further comprising providing a control signal to the tunable AND gate, wherein the control signal provides dead-band control.

9. The method of claim 1 , wherein the compare element comprises a phase detector.

10. The method of claim 9 , further comprising providing an input to the phase detector that determines sensitivity of the phase detector.

11. The method of claim 9 , further comprising providing an input to the phase detector that determines dead-band of the phase detector.

12. The method of claim 1 , further comprising logging a pass or a fail based on the comparing the expected value to the output of the compare element.

13. The method of claim 1 , wherein the connecting the second phase source comprises controlling a plurality of switches to:
connect the one of the plurality of phase rotators to the second input; and
disconnect all of the plurality of phase rotators, other than the one of the plurality of phase rotators, from the second input while the one of the plurality of phase rotators is connected to the second input.

14. The method of claim 1 , wherein the first phase source comprises an output of a phase locked loop (PLL) that is separate from the plurality of phase rotators and that is selectively connected to, and disconnected from, the first input using a switch.

15. The method of claim 14 , further comprising:
providing the output of the PLL as input to a test phase rotator; and
providing an output of the test phase rotator as input to the PLL.

16. The method of claim 1 , wherein:
the compare element receives a control signal separate from the first input and the second input; and
the compare element comprises tunable logic, and the control signal provides control to the tunable logic including one of: timing control; minimum pulse width control; and dead-band control.

17. A method of testing a plurality of phase rotators, comprising:
connecting a first phase source to a first input of a compare element, wherein the first phase source comprises an output of one the plurality of phase rotators that are selectively connectable to the first input;
connecting a second phase source to a second input of the compare element, wherein the second phase source comprises an output of another one the plurality of phase rotators that are selectively connectable to the second input;
generating an expected value of a phase relationship between the first phase source and the second phase source;
comparing the expected value to an output of the compare element; and
logging a pass or a fail based on the comparing the expected value to the output of the compare element.

18. The method of claim 17 , further comprising providing a control signal to the compare element, wherein:
the control signal is separate from the first input and the second input,
the control signal provides control to tunable logic of the compare element, and
the control includes one of: timing control; minimum pulse width control; and dead-band control.

19. A method of testing a plurality of phase rotators, comprising:
connecting an output of a first one of the plurality of phase rotators to a first input of a compare element;
connecting an output of a second one of the plurality of phase rotators to a second input of the compare element;
generating an expected value of a phase relationship between the output of the first one of the plurality of phase rotators and the output of the second one of the plurality of phase rotators;
comparing the expected value to an output of the compare element; and
determining a pass or a fail based on the comparing.

20. The method of claim 19 , further comprising providing a control signal to the compare element, wherein:
the control signal is separate from the first input and the second input,
the control signal provides control to tunable logic of the compare element, and
the control includes one of: timing control; minimum pulse width control; and dead-band control.

Assignees

• IBM

Inventors

• Gerowitz Robert G
• Higgins Sarah B
• Iadanza Joseph A

Classifications

• H04L7/042

  Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• G01R29/18

  Indicating phase sequence; Indicating synchronism · CPC title

• G01R31/31707

  Test strategies (methods for generation of test sequences G01R31/318371) · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title