Integrated structures and methods of forming integrated structures

Patent metadata

Field	Value
Publication number	US-10580792-B2
Application number	US-201816107294-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Jun 20, 2016
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

First claim

We claim:

1. An integrated structure, comprising:
a pair of conductive levels; one of the conductive levels of said pair being a first conductive level and the other of the conductive levels of said pair being a second conductive level;
an intervening insulative level between the first and second conductive levels;
an opening extending through the first conductive level, the intervening insulative level, and the second conductive level; the first conductive level having a first face along the opening, and the second conductive level having a second face along the opening;
a nitride structure within the opening; and
detectable oxide between the nitride structure and the first and second faces of the first and second conductive levels; the detectable oxide being in the form of an oxide liner that extends from the first conductive level to the second conductive level, and that bridges across the intervening insulative level; the oxide liner being along only portions of the first and second faces of the first and second conductive levels.

2. The integrated structure of claim 1 wherein the first and second conductive levels comprise conductively-doped silicon, and wherein the intervening insulative level comprises silicon dioxide.

3. The integrated structure of claim 1 wherein the detectable oxide is along a first side of the nitride structure; wherein a second oxide is along a second side of the nitride structure; and wherein the second side is in opposing relation to the first side.

4. The integrated structure of claim 1 wherein the opening has a width of from about 700 Å to about 3500 Å; and wherein the nitride structure has a wall thickness of from about 50 Å to about 200 Å.

5. The integrated structure of claim 1 wherein the oxide liner has about a same thickness along the intervening insulative level as along the first and second faces of the first and second conductive levels.

6. An integrated structure, comprising:
a metal-containing source material;
a select device gate material over the metal-containing source material and spaced from the metal-containing source material by an insulative material;
vertically-stacked conductive levels over the select device gate material; the vertically-stacked conductive levels including a first conductive level and a second conductive level;
a first opening extending through the vertically-stacked levels to the metal-containing source material; the first opening having opposing sidewalls along a cross-section; the opposing sidewalls being a first sidewall and a second sidewall;
a nitride liner along the opposing sidewalls of the first opening and narrowing the first opening to form a second opening; and
an oxide bridge extending from the first conductive level to the second conductive level, the oxide bridge being along the first sidewall and being between the nitride liner and the first sidewall; the oxide bridge having a first side directly against the first and second conductive levels, and having an opposing second side directly against the nitride liner.

7. The integrated structure of claim 6 comprising vertically-stacked memory cells along the conductive levels; wherein the memory cells are part of an integrated memory structure; and wherein the first opening is a slit utilized to physically define a block within the integrated memory structure.

8. The integrated structure of claim 7 wherein the memory structure comprises NAND.

9. The integrated structure of claim 6 comprising an oxide fill within the second opening, and wherein the oxide fill comprises silicon dioxide.

10. The integrated structure of claim 6 wherein the vertically-stacked levels of conductive material are spaced from one another by intervening levels of oxide.

11. The integrated structure of claim 6 wherein the nitride liner comprises one or both of silicon nitride and silicon oxynitride.

Assignees

• Micron Technology Inc

Inventors

• Li Jie
• Mathew James
• Shrotri Kunal
• Tran Luan C
• Haller Gordon A
• Zhang Yangda
• Yu Hongpeng
• Lee Minsoo

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H05K999/99

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic