Display panel and driving method therefor, and display apparatus

Patent metadata

Field	Value
Publication number	US-10580379-B2
Application number	US-201816041166-A
Country	US
Kind code	B2
Filing date	Jul 20, 2018
Priority date	Jan 3, 2018
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A display panel and a driving method therefor and a display apparatus are provided. The display panel includes a plurality of gate lines and a plurality of data lines, which intersect with each other, each of the data lines has an input terminal, and input terminals of the data lines are provided at a first side of the display panel, the driving method comprises: sequentially applying a gate signal to each of the gate lines, and applying data signals to the data lines through the input terminals while any of the gate lines is applied with a gate signal, wherein the gate signal satisfies conditions that Ta(i)≤Ta(i+1) and Ta(1)<Ta(n), where Ta(i) is a duration of the gate signal applied to the ith gate line starting from the first side, 1≤i≤n−1, where n is a total number of the gate lines.

First claim

The invention claimed is:

1. A method for driving a display panel, wherein the display panel includes a plurality of gate lines and a plurality of data lines, which intersect with each other, each of the data lines has an input terminal, and input terminals of the data lines are provided at a first side of the display panel, the method comprises:
sequentially applying gate signals to the gate lines, and applying data signals to the data lines through the input terminals while any of the gate lines is applied with a gate signal,
the gate signal satisfies conditions that Ta(i)≤Ta(i+1), and Ta(1)<Ta(n), where Ta(i) is a duration of the gate signal applied to the i th gate line starting from the first side, 1≤i≤n−1, where n is a total number of the gate lines,
wherein driving information of the i th gate line starting from the first side includes a duration of a frame of picture Tt, a total number of the gate lines n, and a number of dummy gate lines nb(i), and
the duration of the gate signal applied to the i th gate line is Ta(i)=Tt/[n+nb(i)].

2. The method according to claim 1 , wherein Ta(i)<Ta(i+1).

3. The method according to claim 2 , wherein Ta(i+1)−Ta(i)=ΔT, where ΔT is a fixed value.

4. The method according to claim 3 , wherein the display panel includes a data memory in which driving information corresponding to each gate line is stored, and the driving information includes a duration of the gate signal applied to the gate line, and sequentially applying the gate signals to the gate lines comprises:
prior to applying the gate signal to the gate line, searching the data memory for driving information corresponding to the gate line, and applying the gate signal to the gate line according to the duration of the gate signal to be applied to the gate line in the driving information.

5. The method according to claim 3 , wherein the display panel is a liquid crystal display panel.

6. The method according to claim 2 , wherein the display panel includes a data memory in which driving information corresponding to each gate line is stored, and the driving information includes a duration of the gate signal applied to the gate line, and sequentially applying the gate signals to the gate lines comprises:
prior to applying the gate signal to the gate line, searching the data memory for driving information corresponding to the gate line, and applying the gate signal to the gate line according to the duration of the gate signal to be applied to the gate line in the driving information.

7. The method according to claim 2 , wherein the display panel is a liquid crystal display panel.

8. The method according to claim 1 , wherein the display panel includes a data memory in which driving information corresponding to each gate line is stored, and the driving information includes a duration of the gate signal applied to the gate line, and sequentially applying the gate signals to the gate lines comprises:
prior to applying the gate signal to the gate line, searching the data memory for driving information corresponding to the gate line, and applying the gate signal to the gate line according to the duration of the gate signal to be applied to the gate line in the driving information.

9. The method according to claim 1 , wherein the display panel is a liquid crystal display panel.

10. A display panel, comprising:
a plurality of gate lines and a plurality of data lines, which intersect with each other, each of the data lines has an input terminal, and input terminals of the data lines are provided at a first side of the display panel;
a gate line driving device configured to sequentially apply gate signals to the gate lines;
a data line driving device configured to apply data signals to the data lines through the input terminals while any of the gate lines is applied with the gate signal;
a control device configured to control the gate line driving device to sequentially apply the gate signals to the gate lines, and control the gate signal to satisfy conditions that Ta(i)≤Ta(i+1) and Ta(1)<Ta(n), where Ta(i) is a duration of the gate signal applied to the i th gate line starting from the first side, 1≤i≤n−1, where n is a total number of the gate lines,
wherein driving information of the i th gate line starting from the first side includes a duration of a frame of picture Tt, a total number of the gate lines n, and a number of dummy gate lines nb(i), and
the duration of the gate signal applied to the i th gate line is Ta(i)=Tt/[n+nb(i)].

11. The display panel according to claim 10 , wherein Ta(i)<Ta(i+1).

12. The display panel according to claim 11 , wherein Ta(i+1)−Ta(i)=ΔT, where ΔT is a fixed value.

13. A display device, comprising the display panel of claim 12 .

14. A display device, comprising the display panel of claim 11 .

15. The display panel according to claim 10 , wherein the control device includes:
a data memory configured to store driving information corresponding to each gate line, the driving information including a duration of the gate signal applied to the gate line;
a timing controller configured to search the data memory for the driving information corresponding to the gate line prior to applying the gate signal to the gate line, and control the gate line driving device to apply the gate signal to the gate line according to the duration of the gate signal to be applied to the gate line in the driving information.

16. A display device, comprising the display panel of claim 15 .

17. The display panel according to claim 10 , wherein the display panel is a liquid crystal display panel.

18. A display device, comprising the display panel of claim 10 .

19. The display device according to claim 18 , wherein the display panel is a liquid crystal display panel.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Zhang Zhiwei
• Feng Xia

Classifications

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title