Near-memory hardened compute blocks for configurable computing substrates

Patent metadata

Field	Value
Publication number	US-10579557-B2
Application number	US-201815872943-A
Country	US
Kind code	B2
Filing date	Jan 16, 2018
Priority date	Jan 16, 2018
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A configurable computing system which uses near-memory and in-memory hardened logic blocks is described herein. The hardened logic blocks are incorporated into memory modules. The memory modules include an interface or communication logic to communicate between the configurable computing substrate and the memory module. In an implementation, the memory modules can include an on-die memory or other forms of non-configurable logic to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include an on-die memory and a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations.

First claim

What is claimed is:

1. A configurable computing platform, comprising:
a configurable computing substrate; and
a memory module connected to the configurable computing substrate, the memory module including a memory die and a base die,
wherein the base die includes:
an on-die memory that is communicatively coupled to the configurable computing substrate interface;
a configurable computing substrate interface that is communicatively coupled to the configurable computing substrate;
a memory interface that is communicatively coupled to the memory die and the configurable computing substrate interface; and
a hardened logic block that is communicatively coupled to the on-die memory and the memory interface;

wherein the hardened logic block is configured to:
generate a computation result based on data sent by the configurable computing substrate, and
selectively store the computation result in the memory die or the on-die memory based on an amount of data contained in the computation result.

2. The configurable computing platform of claim 1 , wherein the hardened logic block is at least one of: a central processing unit (CPU), a CPU core, a graphics processing unit (GPU), a GPU core, a hard-coded accelerator, an application specific integrated circuit block, an execution engine, and a data-parallel floating-point-capable execution engine.

3. The configurable computing platform of claim 1 , wherein the on-die memory is configured to communicate with the memory interface and functions as a cache for the memory die.

4. The configurable computing platform of claim 1 , wherein the on-die memory is included in an address range of the memory module.

5. The configurable computing platform of claim 1 , wherein the data from the configurable computing substrate is written to the on-die memory when a size of the data is matched with a capacity of the on-die memory.

6. The configurable computing platform of claim 1 , wherein the computation result is written to the on-die memory when a data size of the computation result is matched with a capacity of the on-die memory.

7. The configurable computing platform of claim 1 , the base die further comprising:
a configurable computing substrate fabric that is communicatively coupled to the configurable computing substrate interface and the hardened logic block.

8. The configurable computing platform of claim 7 , wherein the configurable computing substrate sends the data to the hardened logic block via the configurable computing substrate fabric based on a type of computation.

9. The configurable computing platform of claim 1 , wherein the base die is a logic die.

10. The configurable computing platform of claim 1 , wherein the base die and the memory die are vertically stacked.

11. A method for computing using a configurable computing platform, the method comprising:
receiving, by a memory module, data from a configurable computing substrate, wherein the memory module includes a memory die and a base die;
accessing, by a hardened logic block of the base die, the data via a memory interface of the base die;
generating, by the hardened logic block, a computation result based on the data; and
selectively writing, by the hardened logic block, the computation result to the memory die or an on-die memory of the base die.

12. The method of claim 11 , further comprising:
writing the data to the on-die memory when a size of the data is matched with a capacity of the on-die memory.

13. The method of claim 11 ,
wherein the computation result is written to the on-die memory when a data size of the computation result is matched with a capacity of the on-die memory.

14. The method of claim 12 , further comprising:
writing a portion of the data to the on-die memory when the data is being written to the memory the; and
servicing subsequent reads to the portion of the data.

15. The method of claim 12 , wherein the on-die memory is included in an address range of the memory module.

16. The method of claim 11 , further comprising:
communicating the data between the configurable computing substrate and the hardened logic block via a configurable computing substrate fabric and the configurable computing substrate interface based on a type of computation, the configurable computing substrate fabric being provided on the die.

17. The method of claim 16 , further comprising:
writing the data to the on-die memory via the configurable computing substrate interface when a size of the data is matched with a capacity of the on-die memory, the on-die memory being provided on the die.

Assignees

• Advanced Micro Devices Inc

Inventors

• Jayasena Nuwan
• Ignatowski Michael

Classifications

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F13/1694 Primary

  Configuration of memory controller to different memory types · CPC title

• G06F3/065

  Replication mechanisms · CPC title

• G06F3/068

  Hybrid storage device · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title