Semiconductor device

Patent metadata

Field	Value
Publication number	US-10579302-B2
Application number	US-201615051256-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Oct 20, 2015
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A semiconductor device includes a first substrate on which an interface unit connectable to a host device is provided, a first memory module on the first substrate, and a first controller on the first substrate. The first controller includes a control unit that controls the first memory module, and a switching unit that switches an operation mode in response to a command from the host device. A first connecting portion is provided on the first substrate and is electrically connected to the first memory module and the first controller. The first controller can directly access a second memory module through the first connecting portion. Thus, for example the first controller can read data stored in the second memory module depending on operation mode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first circuit board substrate;
a plurality of terminals along a first edge portion of the first circuit board substrate, the plurality of terminals being connectable to a host device;
a first memory module on a surface of the first circuit board substrate; and
a first controller on the surface of the first circuit board substrate and spaced from the first memory module in a direction parallel to the surface, the first controller configured to:
control the first memory module, and
switch an operation mode in response to a command from the host device such that in a first operation mode the first controller reads data from the first memory module and in a second operation mode the first controller reads data from a second memory module on a second circuit board substrate spaced from the first circuit board

wherein, when in the second operation mode, the first controller accesses the second memory module directly through a first connecting portion that is away from the first edge portion of the first circuit board substrate.

2. The semiconductor device according to claim 1 , wherein the first connection portion comprises a connector and a harness.

3. The semiconductor device according to claim 2 , wherein the connector is on the surface of the first circuit board substrate.

4. The semiconductor device according to claim 2 , wherein the connector is on a device to which the first circuit board substrate is mounted.

5. The semiconductor device according to claim 1 , wherein the first controller is configured to read data from the second memory module and write the data to the first memory module.

6. The semiconductor device according to claim 5 , wherein the first controller is configured to receive a command from the host device to read data from the second memory module, then check whether writing data to the first memory module is possible, and then to write data read from the second memory module to the first memory module if possible.

7. The semiconductor device according to claim 6 , wherein, if the writing of data to the first memory module is not possible, the first controller is configured to transmit the data read from the second memory module to the host device via the plurality of terminals.

8. The semiconductor device according to claim 6 , wherein when the writing of data to the first memory module is not possible, the first controller is configured to perform a garbage collection process on the first memory module.

9. The semiconductor device according to claim 1 , wherein the second circuit board substrate includes a second controller mounted thereon, and
the first and second circuit board substrates are substantially identical to each other.

10. An electronic device, comprising:
a host device board including a first interface connector and a second interface connector;
a first circuit board substrate connected to the first interface connector and including a first memory module, a first controller, and a first pass-through connector disposed thereon;
a second circuit board substrate connected to the second interface connector and including a second memory module, a second controller, and a second pass-through connector disposed thereon, wherein
the first and second circuit board substrates are physically spaced from each other on the host device board,
a direct electrical connection pathway is provided between the first and second circuit board substrates via the first pass-through connector and the second pass-through connector, and
the first controller includes a first processor unit, a first host interface unit, and a first memory interface unit, and is configured to switch between a first operating mode and a second operating mode according to a command from a host device such that in the first operating mode the first controller reads data from the first memory module and in the second operating mode the first controller reads data from the second memory module via the direct electrical connection pathway.

11. The electronic device according to claim 10 , wherein the first controller is configured to write data read from the second memory module to the first memory module.

12. The electronic device according to claim 10 , wherein the first controller is configured to transmit data read from the second memory module to the host device.

13. The electronic device according to claim 10 , wherein the first memory module comprises a flash memory.

14. The electronic device according to claim 10 , wherein the first and second circuit board substrates are solid-state storage device cards.

15. The electronic device according to claim 10 , wherein the first and second interface connectors each comprise a connector slot in to which the first and second circuit board substrates are inserted.

16. The electronic device according to claim 10 , wherein the second controller includes a second processor unit, a second host interface unit, and a second memory interface unit, and is configured to switch between a first operating mode and a second operating mode according to a command from the host device such that in the first operating mode the second controller reads data from the second memory module and in the second operating mode the second controller reads data from the first memory module via the direct electrical connection.

17. The electronic device according to claim 10 , wherein the first circuit board substrate and the first interface connector conform to a PCI Express standard.

18. A semiconductor device, comprising:
a first memory module having a first connection pathway to a host device;
a second memory module having a second connection pathway to the host device; and
a memory controller configured to access the first memory module and to perform switching so as to directly access the second memory module via a third connection pathway according to a predetermined condition, the third connection pathway not including any portions of the first and second connection pathways.

19. The semiconductor device according to claim 18 , wherein
the first and second memory modules are on different substrates physically separated from each other, comprise flash-type memory, and
the predetermined condition is receipt of a command from the host device by the memory controller, the command requesting data be read from the second memory module.

20. The semiconductor device according to claim 19 , wherein the third connection pathway comprises a wiring spanning a gap between the different substrates.

Assignees

• Toshiba Memory Corp

Inventors

• Nakata Hiroki
• Matsumoto Manabu

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F3/0664

  at device level, e.g. emulation of a storage device or system · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F13/4068

  Electrical coupling · CPC title