Memory device and reclaiming method of the memory device

Patent metadata

Field	Value
Publication number	US-10579286-B2
Application number	US-201816120832-A
Country	US
Kind code	B2
Filing date	Sep 4, 2018
Priority date	Nov 13, 2017
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A memory device includes a nonvolatile memory having a first block and a memory controller configured to exchange data with the nonvolatile memory. The memory controller includes a first processor to divide the first block into first and second domains, a second processor to generate a reclaim signal by determining whether to perform reclaiming on each of the first and second domains and a third processor performer which reclaims each of the first and second domains according to the reclaim signal and merges the first and second domains.

First claim

What is claimed is:

1. A memory device comprising:
a nonvolatile memory comprising a first block; and
a memory controller configured to exchange data with the nonvolatile memory,
wherein the memory controller comprises:
a first processor which divides the first block into first and second domains;
a second processor which generates a reclaim signal by determining whether to perform reclaiming on each of the first and second domains; and
a third processor which reclaims each of the first and second domains according to the reclaim signal and merges the first and second domains.

2. The memory device of claim 1 , wherein the first block comprises a plurality of pages, and the first processor calculates a first score for each of the pages by using first information and assigns each of the pages to the first or second domain by comparing the first score with a preset first reference score.

3. The memory device of claim 2 , wherein the first information comprises at least one of physical characteristics, read count, elapsed time after writing and error check & correction (ECC) information of each of the pages.

4. The memory device of claim 2 , wherein the first processor updates the first information and newly divides the first block into the first and second domains using the updated first information.

5. The memory device of claim 1 , wherein the third processor reorders the first and second domains when merging the first and second domains.

6. The memory device of claim 1 , wherein the nonvolatile memory comprises a second block, the first processor divides the second block into third and fourth domains, the third processor generates a second reclaim signal by determining whether to perform reclaiming on each of the third and fourth domains, and the third processor reclaims at least one of the third and fourth domains according to the second reclaim signal and merges the third and fourth domains.

7. The memory device of claim 1 , wherein the second processor generates a first score using first information and determines whether to perform the reclaiming by comparing the first score with a preset first reference score.

8. The memory device of claim 7 , wherein the first information comprises at least one of ECC information, dispersion information, structural characteristics, an input/output flow, and external stress.

9. A memory device comprising:
a nonvolatile memory comprising a first data block, a first free block and a second free block; and
a memory controller configured to exchange data with the nonvolatile memory,
wherein the memory controller divides the first block into first and second domains having first and second data, respectively, transfers the first data to the first free block, transfers the second data to the second free block, and merges the first and second data by transferring the first data to the second free block.

10. The memory device of claim 9 , wherein a physical address of each of the first domain and the second domain is discontinuous.

11. The memory device of claim 9 , wherein the transferring of the first data to the first free block comprises copying the first data to the first free block and marking the first data in the first block as invalid.

12. The memory device of claim 11 , wherein the transferring of the second data to the second free block by the memory controller comprises copying the second data to the second free block and marking the second data in the second block as invalid.

13. The memory device of claim 11 , wherein the memory controller determines whether to reclaim each of the first and second domains and transfers the first data when determining to reclaim the first domain.

14. The memory device of claim 13 , wherein the second data is transferred when the memory controller determines it is to reclaim the second domain.

15. A reclaiming method of a memory device, the method comprising:
dividing, by a first processor of a memory controller, a first block into first and second domains having first and second data, respectively;
generating, by a second processor of the memory controller, a reclaim signal by determining whether to reclaim each of the first and second domains;
reclaiming, by a third processor of the memory controller, the first domain according to the reclaim signal;
reclaiming, by the memory controller, the second domain according to the reclaim signal; and
merging, by the memory controller, the first domain and the second domain.

16. The method of claim 15 , wherein the reclaiming of the first domain comprises the third processor copying the first data to a first free block and marking the first data in the first block as invalid.

17. The method of claim 16 , wherein the reclaiming of the second domain comprises:
copying, by the third processor, the second data from the first block to a second free block and marking the second data in the second domain as invalid; and
copying, by the third processor, the first data of the first free block to the second domain and marking the first data in the first free block as invalid.

18. The method of claim 15 , wherein the merging of the first domain and the second domain comprises merging the first and second data by reordering the first and second data.

19. The method of claim 15 , wherein the dividing of the first block into the first and second domains is performed using first information, wherein the first information comprises at least one of physical characteristics, read count, elapsed time after writing and ECC information of each of a plurality of pages of the first block.

20. The method of claim 19 , wherein the first information is updated periodically, and the first block is divided into the first and second domains based on the updated first information.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Hee-Tai
• Jun Walter

Classifications

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title