Envelope-tracking control techniques for highly-efficient RF power amplifiers

Patent metadata

Field	Value
Publication number	US-10574187-B2
Application number	US-201515777744-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Dec 21, 2015
Publication date	Feb 25, 2020
Grant date	Feb 25, 2020

Abstract

Envelope-tracking control techniques are disclosed for highly-efficient radio frequency (RF) power amplifiers. In some cases, a III-V semiconductor material (e.g., GaN or other group III material-nitride (III-N) compounds) MOSFET including a high-k gate dielectric may be used to achieve such highly-efficient RF power amplifiers. The use of a high-k gate dielectric can help to ensure low gate leakage and provide high input impedance for RF power amplifiers. Such high input impedance enables the use of envelope-tracking control techniques that include gate voltage (Vg) modulation of the III-V MOSFET used for the RF power amplifier. In such cases, being able to modulate Vg of the RF power amplifier using, for example, a voltage regulator, can result in double-digit percentage gains in power-added efficiency (PAE). In some instances, the techniques may simultaneously utilize envelope-tracking control techniques that include drain voltage (Vd) modulation of the III-V MOSFET used for the RF power amplifier.

First claim

What is claimed is:

1. An integrated circuit including at least one transistor, the integrated circuit comprising:
a body including group III-V semiconductor material;
a gate electrode at least above the body, the gate electrode including one or more metals;
a first layer between the body and the gate electrode, the first layer comprising at least one of aluminum nitride, aluminum indium nitride, aluminum gallium nitride, and aluminum indium gallium nitride;
a second layer between the first layer and the gate electrode, the second layer including one or more high-k dielectrics; and
a source region and a drain region, the source and drain regions adjacent to the body, the source and drain regions including semiconductor material.

2. The integrated circuit of claim 1 , wherein the second layer is conformal to and directly in contact with at least a portion of the source and drain regions.

3. The integrated circuit of claim 1 , wherein the gate electrode is electrically connected to a voltage regulator.

4. The integrated circuit of claim 1 , wherein the group III-V semiconductor material included in the body includes nitrogen.

5. The integrated circuit of claim 4 , wherein the group III-V semiconductor material included in the body further includes gallium.

6. The integrated circuit of claim 1 , wherein the second layer includes two or more high-k dielectrics that are compositionally different.

7. The integrated circuit of claim 1 , wherein the one or more high-k dielectrics included in the second layer includes oxygen or silicon, or both oxygen and silicon.

8. The integrated circuit of claim 7 , wherein the one or more high-k dielectrics included in the second layer includes hafnium.

9. The integrated circuit of claim 1 , wherein the second layer has a thickness between the body and the gate electrode of less than 10 nanometers.

10. The integrated circuit of claim 1 , further comprising a third layer between portions of the first and second layers, the third layer including aluminum, indium, and nitrogen.

11. The integrated circuit of claim 1 , wherein the gate electrode includes one or more of titanium, nickel, and gold.

12. The integrated circuit of claim 1 , wherein the drain region is electrically connected to a voltage regulator.

13. The integrated circuit of claim 1 , wherein the source and drain regions further include n-type dopant.

14. The integrated circuit of claim 1 , wherein the body is a fin, the fin between two portions of the gate electrode.

15. The integrated circuit of claim 1 , wherein the gate electrode is around the body.

16. A computing system comprising the integrated circuit of claim 1 .

17. An integrated circuit including at least one transistor, the integrated circuit comprising:
a body including gallium and nitrogen;
a gate electrode at least above the body, the gate electrode including one or more metals;
a first layer between the body and the gate electrode, the first layer including aluminum and nitrogen;
a second layer between the first layer and the gate electrode, the second layer including one or more high-k dielectrics;
a third layer between portions of the first and second layers, the third layer including aluminum, indium, and nitrogen; and
a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material;
wherein the gate electrode is electrically connected to a voltage regulator.

18. The integrated circuit of claim 17 , further comprising a third layer between the second layer and the gate electrode, the third layer include one or more high-k dielectrics, wherein the second and third layers include compositionally different material.

19. The integrated circuit of claim 17 , wherein the first layer includes a thickness between 0.5 and 3 nanometers.

20. The integrated circuit of claim 10 , wherein the first layer comprises aluminum nitride.

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Sung Seung Hoon
• Gardner Sanaz K

Classifications

• H03F2200/15

  the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal · CPC title

• H03F2200/105

  A non-specified detector of the power of a signal being used in an amplifying circuit · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03F1/0222 Primary

  by using a signal derived from the input signal · CPC title