Isolated synchronous rectifying DC/DC converter

US10566910B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10566910-B2
Application numberUS-201916246816-A
CountryUS
Kind codeB2
Filing dateJan 14, 2019
Priority dateJan 17, 2018
Publication dateFeb 18, 2020
Grant dateFeb 18, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A synchronous rectification controller includes: a drain terminal connected to a drain of a synchronous rectification transistor; a first comparator configured to compare a drain voltage of the drain terminal with a first threshold voltage; a second comparator configured to compare the drain voltage of the drain terminal with a second threshold voltage; a flip-flop to which an ON signal output from the first comparator and an OFF signal output from the second comparator are input; a driver configured to output a gate signal to the synchronous rectification transistor based on an output signal of the flip-flop; and a threshold adjusting part configured to adjust the second threshold voltage based on the drain voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. An isolated synchronous rectifying DC/DC converter configured as an LLC converter, the DC/DC converter comprising: a synchronous rectification transistor disposed on a secondary side of the DC/DC converter; and a synchronous rectification controller configured to control driving of the synchronous rectification transistor, wherein the synchronous rectification controller includes: a drain terminal connected to a drain of the synchronous rectification transistor; a first comparator configured to compare a drain voltage of the drain terminal with a first threshold voltage; a second comparator configured to compare the drain voltage of the drain terminal with a second threshold voltage; a flip-flop to which an ON signal output from the first comparator and an OFF signal output from the second comparator are input; a driver configured to output a gate signal to the synchronous rectification transistor based on an output signal of the flip-flop; and a threshold adjusting part configured to adjust the second threshold voltage based on the drain voltage, and wherein the threshold adjusting part includes a sample hold circuit configured to sample and hold the drain voltage, and is configured to adjust the second threshold voltage based on a sampling voltage output from the sample hold circuit. 2. The DC/DC converter of claim 1 , wherein the threshold adjusting part further includes at a front stage of the sample hold circuit: a V/I conversion circuit configured to perform voltage-current conversion on the drain voltage; a first current mirror circuit receiving an output of the V/I conversion circuit as an input current; and a first resistor through which an output current of the first current mirror circuit flows. 3. The DC/DC converter of claim 1 , wherein the threshold adjusting part includes a delay circuit to which an output of the flip-flop is input, and wherein a sampling mode and a hold mode of the sample hold circuit are switched according to a delayed signal output from the delay circuit. 4. The DC/DC converter of claim 3 , wherein a delay time of the delay circuit is near half of a period of a current flowing through the synchronous rectification transistor. 5. The DC/DC converter of claim 1 , wherein the synchronous rectification controller further includes a threshold setting terminal to which a setting resistor is connected, wherein the threshold adjusting part further includes a constant voltage circuit configured to control an output voltage to the sampling voltage, and wherein the output voltage is applied to the threshold setting terminal. 6. The DC/DC converter of claim 5 , wherein the threshold adjusting part further includes: a second current mirror circuit receiving a current flowing through the setting resistor as an input current; and a second resistor through which an output current of the second current mirror circuit flows so that a predetermined voltage is applied to one end of the second resistor. 7. An isolated synchronous rectifying DC/DC converter configured as an LLC converter, the DC/DC converter comprising: a synchronous rectification transistor disposed on a secondary side of the DC/DC converter; and a synchronous rectification controller configured to control driving of the synchronous rectification transistor, wherein the synchronous rectification controller includes: a drain terminal connected to a drain of the synchronous rectification transistor; a first comparator configured to compare a drain voltage of the drain terminal with a first threshold voltage; a second comparator configured to compare the drain voltage of the drain terminal with a second threshold voltage; a flip-flop to which an ON signal output from the first comparator and an OFF signal output from the second comparator are input; a driver configured to output a gate signal to the synchronous rectification transistor based on an output signal of the flip-flop; and a threshold adjusting part configured to adjust the second threshold voltage based on the drain voltage, and wherein the threshold adjusting part is disposed between the drain terminal and the second comparator. 8. An isolated synchronous rectifying DC/DC converter configured as an LLC converter, the DC/DC converter comprising: first and second synchronous rectification transistors disposed on a secondary side of the DC/DC converter; and a synchronous rectification controller configured to control driving of the first and second synchronous rectification transistors, wherein the synchronous rectification controller includes: first and second drain terminals connected to drains of the first and second synchronous rectification transistors, respectively; a first comparator configured to compare the drain voltages of the first and second drain terminals with a first threshold voltage; a second comparator configured to compare the drain voltages of the first and second drain terminals with a second threshold voltage; a flip-flop to which an ON signal output from the first comparator and an OFF signal output from the second comparator are input; first and second drivers configured to output gate signals to the first and second synchronous rectification transistors, respectively, based on an output signal of the flip-flop; a selector having an output terminal connected to the first and second comparators and an input terminal to which the output signal of the flip-flop is input, and configured to perform: a first operation of switching between conduction of a path from the first drain terminal to the output terminal and conduction of a path from the second drain terminal to the output terminal; and a second operation of switching between conduction of a path from the input terminal to the first driver and conduction of a path from the input terminal to the second driver; and a threshold adjusting part configured to adjust the second threshold voltage based on the drain voltages. 9. The DC/DC converter of claim 8 , further comprising a frequency divider configured to output a frequency divider output signal according to the output signal of the flip-flop, wherein the selector performs the first and second operations based on the frequency divider output signal. 10. The DC/DC converter of claim 9 , wherein the frequency divider output signal is switched between a high level and a low level at every falling timing of the output signal of the flip-flop. 11. The DC/DC converter of claim 8 , wherein the threshold adjusting part includes a sample hold circuit configured to sample and hold the drain voltages, and is configured to adjust the second threshold voltage based on a sampling voltage output from the sample hold circuit. 12. The DC/DC converter of claim 11 , wherein the threshold adjusting part further includes at a front stage of the sample hold circuit: a V/I conversion circuit configured to perform voltage-current conversion on the drain voltages; a first current mirror circuit receiving an output of the V/I conversion circuit as an input current; and a first resistor through which an output current of the first current mirror circuit flows. 13. The DC/DC converter of claim 11 , wherein the threshold adjusting part includes a delay circuit to which an output of the flip-flop is input, and wherein a sampling mode and a hold mode of the sample hold circuit are switched according to a delayed signal output from the delay circuit. 14. The DC/DC converter of claim 13 , wherein a delay time of the delay circuit is near half of a period of a current flowing through the synchronous rectification tra

Assignees

Inventors

Classifications

  • having at least one active switching element at the secondary side of an isolation transformer · CPC title

  • having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer · CPC title

  • the control signals being transmitted optically · CPC title

  • Details of control, feedback or regulation circuits · CPC title

  • Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

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What does patent US10566910B2 cover?
A synchronous rectification controller includes: a drain terminal connected to a drain of a synchronous rectification transistor; a first comparator configured to compare a drain voltage of the drain terminal with a first threshold voltage; a second comparator configured to compare the drain voltage of the drain terminal with a second threshold voltage; a flip-flop to which an ON signal output …
Who is the assignee on this patent?
Rohm Co Ltd
What technology area does this patent fall under?
Primary CPC classification H02M3/33592. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 18 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).