Power semiconductor device with floating field ring termination

Patent metadata

Field	Value
Publication number	US-10566463-B2
Application number	US-201916420803-A
Country	US
Kind code	B2
Filing date	May 23, 2019
Priority date	Nov 24, 2016
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

In a power semiconductor device of the application a total number n of floating field rings (10_1 to 10_n) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation di,i−i between an i-th floating field ring and a directly adjacent (i−1)-th floating field ring, when counting the floating field rings (10_1 to 10_n) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: di,i−1=d1,0+Σj=1j=i−1 Δj for i=2 to n, wherein d1,0 is a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: Δzone1−0.05·Δzone2<Δj<Δzone1+0.05·Δzone2 for j=1 to I−2, 2·Δzone2<|Δj|<10·Δzone2. for j=I−1, 0.95·Δzone2<Δj<1.05·Δzone2 for j=I to n−1, Δzone2>0.1 μm, and −Δzone2/2<Δzone1<Δzone2/2, wherein I is an integer, for which 3≤l≤n/2.

First claim

The invention claimed is:

1. A power semiconductor device comprising:
a wafer, the wafer having an active area and a termination area laterally surrounding the active area, wherein a main pn-junction is formed in the active area, and
a plurality of floating field rings formed in the termination area, each floating field ring laterally surrounding the active area, wherein a total number of floating field rings formed in the termination area is n,
wherein, for any integer i in a range from i=2 to i=n, a distance between an i-th floating field ring ( 10 _ i ), and a directly adjacent (i−1)-th floating field ring ( 10 _ i− 1), when counting the floating field rings ( 10 _ 1 to 10 _ n ) along a straight line starting from the main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula:
d i,i−1 =d 1,0 +Σ j=1 j=i−1 Δ j for i= 2 to n,

wherein d 1,0 is a distance between the innermost floating field ring ( 10 _ 1 ) directly adjacent to the main pn-junction and the main pn-junction, and wherein:
Δ zone1 −0.05·Δ zone2 <Δ j <Δ zone1 +0.05·Δ zone2 for j= 1 to l− 2,

|Δ j |<10·Δ zone2· for j=l− 1,

0.95·Δ zone2 <Δ j <1.05·Δ zone2 for j=l to n− 1,

Δ zone2 >0.1 μm, −Δ zone2 /2<Δ zone1 <Δ zone2 /2, and

wherein j and I are integers, and
3≤ l≤n/ 2,

wherein n is at least 10 and
2·Δ zone2 <|Δ j | for j=l− 1.

2. The power semiconductor device according to claim 1 , wherein
−10·Δ zone2 <Δ j <−2·Δ zone2· for j=l− 1.

3. The power semiconductor device according to claim 1 , wherein
2·Δ zone2 <Δ j <10·Δ zone2· for j=l− 1.

4. The power semiconductor device according to claim 1 , wherein
Δ zone1 =0 μm.

5. The power semiconductor device according to claim 1 , wherein
Δ zone2 >0.2 μm.

6. The power semiconductor device according to claim 1 , wherein
4≤ l≤n/ 2, or

5≤ l≤n/ 2.

7. The power semiconductor device according to claim 1 , wherein for any natural number i in a range from 1 to n, a lateral width w i of the i-th floating field ring ( 10 _ i ) from the main pn-junction differs less than 20% from a constant w r .

8. The power semiconductor device according to claim 7 , wherein
0.5 μm≤ w r ≤20 μm, or

1 μm≤ w r ≤20 μm.

9. The power semiconductor device according to claim 1 , wherein:
the wafer has a first main side and a second main side opposite to the first main side,
the wafer comprises a semiconductor layer of a first conductivity type adjacent to the first main side of the wafer,
the floating field rings ( 10 _ 1 to 10 _ n ) are ring-shaped first well regions formed in the semiconductor layer, wherein the first well regions are of a second conductivity type to respectively form first pn-junctions with the semiconductor layer,
the active area is an area of a second well region in the semiconductor layer, wherein the second well region is of the second conductivity type to form the main pn-junction with the semiconductor layer.

10. The power semiconductor device according to claim 9 , wherein a first depth (d r ) of the first well regions is the same for all floating field rings ( 10 _ 1 to 10 _ n ).

11. The power semiconductor device according to claim 10 , wherein a second depth of the second well region is the same as the first depth (d r ) of the first well regions.

12. The power semiconductor device according to claim 1 , wherein
1 μm≤ d 1,0 ≤15 μm.

13. The power semiconductor device according to claim 1 , wherein the total number n of floating field rings ( 10 _ 1 to 10 _ n ) is at least 20.

14. The power semiconductor device according to claim 13 , wherein the total number n of floating field rings ( 10 _ 1 to 10 _ n ) is at least 30.

15. The power semiconductor device according to claim 7 , wherein for any natural number i in a range from 1 to n, a lateral width w i of the i-th floating field ring ( 10 _ i ) from the main pn-junction differs less than 15%-from a constant w r .

16. The power semiconductor device according to claim 2 , wherein
Δ zone1 =0 μm.

17. The power semiconductor device according to claim 2 , wherein
Δ zone2 >0.2 μm.

18. The power semiconductor device according to claim 2 , wherein
4≤ l≤n/ 2, or

5≤ l≤n/ 2.

19. The power semiconductor device according to claim 15 , wherein
0.5 μm≤ w r ≤20 μm, or

1 μm≤ w r ≤20 μm.

20. The power semiconductor device according to claim 2 , wherein:
the wafer has a first main side and a second main side opposite to the first main side,
the wafer comprises a semiconductor layer of a first conductivity type adjacent to the first main side of the wafer,
the floating field rings ( 10 _ 1 to 10 _ n ) are ring-shaped first well regions formed in the semiconductor layer, wherein the first well regions are of a second conductivity type to respectively form first pn-junctions with the semiconductor layer,
the active area is an area of a second well region in the semiconductor layer, wherein the second well region is of the second conductivity type to form the main pn-junction with the semiconductor layer.

Assignees

• Abb Schweiz Ag
• Abb Schweiz

Inventors

• Bauer Friedhelm
• Vemulapati Umamaheswara
• Bellini Marco

Classifications

• H01L29/868

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic

• H01L29/8611 Primary

  Electricity · mapped topic

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8325

  Silicon carbide · CPC title