Semiconductor memory device including 3-dimensional structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10566343-B2
Application number	US-201715803035-A
Country	US
Kind code	B2
Filing date	Nov 3, 2017
Priority date	May 4, 2016
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor memory device, comprising:
forming a peripheral circuit over a substrate comprising, cell regions and a contact region between the cell regions;
forming bottom wiring lines over the peripheral circuit the bottom wiring lines being electrically coupled with the peripheral circuit;
stacking alternating layers of interlayer dielectric layers and sacrificial layers over the bottom wiring lines;
forming a first slit for dividing the interlayer dielectric layers and the sacrificial layers of the contact region into a first portion and a second portion, wherein the first portion is continuous with the interlayer dielectric layers and the sacrificial layers of the cell region, and the second portion is isolated from the first portion and the interlayer dielectric layers and the sacrificial layers of the cell region by the first slit, thereby form a dielectric structure constructed with the second portion;
forming a dielectric sidewall layer which fills the first slit and surrounds the dielectric structure;
forming a second slit through the interlayer dielectric layers and the sacrificial layers;
removing the sacrificial layers which are exposed by the second slit without removing the sacrificial layers included in the dielectric structure using the dielectric sidewall layer as an etching mask;
forming a conductive material in spaces from which the sacrificial layers are removed to thereby form conductive lines;
forming contact plugs electrically coupled with the bottom wiring lines, through the dielectric structure; and
forming top wiring lines electrically coupled with the contact plugs.

2. The method according to claim 1 , further comprising:
forming a through hole passing through the first portion of the interlayer dielectric layers and the sacrificial layers of the contact region, before the forming of the second slit; and
forming a support which fills the through hole.

3. The method according to claim 2 , wherein the forming of the through hole is performed simultaneously with the forming of the first slit.

4. The method according to claim 2 , wherein the forming of the support is performed simultaneously with the forming of the dielectric sidewall layer.

5. The method according to claim 1 , wherein the support and the dielectric sidewall layer are formed of a material which has an etching selectivity different from the sacrificial layers.

6. The method according to claim 5 , Wherein the support and the dielectric sidewall layer are formed of an oxide-based material, and the sacrificial layers are formed of a nitride-based material.

7. The method according to claim 1 , wherein the forming of the second slit is performed such that the interlayer dielectric layers and the sacrificial layers are divided into memory block units by the second slit.

Assignees

• Sk Hynix Inc

Inventors

• Oh Sung-Lae
• Kim Jin-Ho
• Son Chang-Man
• Lee Go-Hyun
• HONG Young-Ock

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic