Method of packaging power semiconductor module including power transistors

Patent metadata

Field	Value
Publication number	US-10566258-B2
Application number	US-201815969897-A
Country	US
Kind code	B2
Filing date	May 3, 2018
Priority date	Jun 30, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor module comprising the steps of:
(a) preparing a first semiconductor chip including a first power transistor therein and having a first surface, a first terminal formed on the first surface and electrically connected to the first power transistor, a second surface opposite to the first surface, and a second terminal formed on the second surface and electrically connected to the first power transistor;
(b) preparing a second semiconductor chip including a second power transistor therein and having a first surface, a third terminal formed the first surface and electrically connected to the second power transistor, a second surface opposite to the first surface, a fourth terminal formed on the second surface and electrically connected to the second power transistor;
(c) after the step (a), mounting the first semiconductor chip through a first conductive bonding material on a first chip mounting portion having a first surface and a second surface opposite to the first surface so that the first surface of the first chip mounting portion and the second surface of the first semiconductor chip face each other;
(d) after the step (b), mounting the second semiconductor chip through a second conductive bonding material on a second chip mounting portion having a first surface and a second surface opposite to the first surface so that the first surface of the second chip mounting portion and the second surface of the second semiconductor chip face each other;
(e) after the steps (c) and (d), electrically connecting the second chip mounting portion and the first terminal of the first semiconductor chip through a first conductive member;
(f) after the steps (c) and (d), electrically connecting a lead and the third terminal of the second semiconductor chip through a second conductive member;
(g) after the steps (e) and (f), sealing the first semiconductor chip, the second semiconductor chip, a part of the first chip mounting portion, a part of the second chip mounting portion, the first conductive member, the second conductive member, and a part of the lead, with a sealing body having a first surface and a second surface opposite to the first surface so that each of the second surface of the first chip mounting portion and the second surface of the second chip mounting portion is exposed from the second surface of the sealing body;
(h) after the step (g), bonding an insulating layer to the second surface of the sealing body so as to cover the second surface of the first chip mounting portion and the second surface of the second chip mounting portion; and
(i) after the step (h), bonding a heat transfer material layer to the insulating layer,
wherein, after the step (i), a region of the heat transfer material layer is included in a region of the insulating layer in a plan view.

2. The method of manufacturing the semiconductor module according to claim 1 ,
wherein, in a plan view, the sealing body includes a first through hole and a second through hole each penetrating from the first surface to the second surface of the sealing body, and
wherein the insulating layer and the heat transfer material layer are located between the first through hole and the second through hole.

3. The method of manufacturing the semiconductor module according to claim 2 ,
wherein a screw member is attached to each of the first through hole and the second through hole, and
wherein the sealing body and a heat sink are bonded to each other by the screw member.

4. The method of manufacturing the semiconductor module according to claim 3 ,
wherein, in a plan view, the insulating layer and the heat transfer material layer are formed to extend over both sides of a virtual line connecting respective centers of the first through hole and the second through hole.

5. The method of manufacturing the semiconductor module according to claim 4 ,
wherein, in a plan view, a distance between the virtual line and one end of the insulating layer arranged in a direction along the virtual line and a distance between the virtual line and the other side of the insulating layer are the same as each other.

6. The method of manufacturing the semiconductor module according to claim 1 ,
wherein, after the step (i), each of the first semiconductor chip and the second semiconductor chip is located inside the region of the heat transfer material layer in a transparent plan view.

7. The method of manufacturing the semiconductor module according to claim 1 , comprising a step of:
after the step (g) and before the step (h), cutting and shaping a part of each of a plurality of the leads exposed from the sealing body.

8. The method of manufacturing the semiconductor module according to claim 1 ,
wherein the semiconductor module further includes a control chip controlling the first semiconductor chip and the second semiconductor chip, and
wherein, in a transparent plan view, the control chip is located in the region of the insulating layer and the region of the heat transfer material layer.

9. The method of manufacturing the semiconductor module according to claim 1 ,
wherein a thickness of each of the first chip mounting portion and the second chip mounting portion is equal to or larger than a thickness of each of the insulating layer and the heat transfer material layer.

10. The method of manufacturing the semiconductor module according to claim 1 ,
wherein the first terminal of the first semiconductor chip is an emitter terminal, and the second terminal of the first semiconductor chip is a collector terminal, and
wherein the third terminal of the second semiconductor chip is an emitter terminal, and the fourth terminal of the second semiconductor chip is a collector terminal.

11. The method of manufacturing the semiconductor module according to claim 1 ,
wherein, after the step (i),
in a plan view, the insulating layer includes: a first side extending in a first direction; a second side opposite to the first side; a third side extending in a second direction crossing the first direction; and a fourth side opposite to the third side,
in a plan view, the heat transfer material layer includes: a fifth side extending in the first direction; a sixth side opposite to the fifth side; a seventh side extending in the second direction; and an eighth side opposite to the seventh side, and
in a plan view, the fifth side of the heat transfer material layer is located between the first side of the insulating layer and the second side of the insulating layer, the sixth side of the heat transfer material layer is located between the second side of the insulating layer and the fifth side of the heat transfer material layer, the seventh side of the heat transfer material layer is located between the third side of the insulating layer and the fourth side of the insulating layer, and the eighth side of the heat transfer material layer is located between the fourth side of the insulating layer and the seventh side of the heat transfer material layer.

12. A method of manufacturing a semiconductor module comprising the steps of:
(a) preparing a first semiconductor chip including a first power transistor therein and having a first surface, a first terminal formed on the first surface and electrically connected to the first power transistor, a second surface opposite to the first surface, and a second terminal formed on the second surface and electrically connected to the first power transistor;
(b) preparing a second semiconductor chip including a second power transistor therein and having a first surface, a third terminal formed on the first surface and electrically connected

Assignees

• Renesas Electronics Corp

Inventors

• Muto Kuniharu
• Bando Koji

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/476

  Organic materials comprising silicon · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title