Processors, methods, systems, and instructions to generate sequences of consecutive integers in numerical order

Patent metadata

Field	Value
Publication number	US-10565283-B2
Application number	US-201113976766-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four consecutive non-negative integers in numerical order. In an aspect, the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. Other methods, apparatus, systems, and instructions are disclosed.

First claim

What is claimed is:

1. A method comprising:
receiving an instruction, the instruction indicating a destination packed data register and indicating a register storing an offset, wherein the instruction does not have an immediate; and
storing a result in the destination packed data register in response to the instruction, the result including a sequence of at least four consecutive non-negative integers in numerical order with a smallest one of the at least four consecutive non-negative integers differing from zero by the offset,
wherein the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location,
wherein storing integers in numerical order is fixed by, and implicit for, an opcode of the instruction, and
wherein the instruction does not indicate a memory location.

2. The method of claim 1 , wherein receiving comprises receiving the instruction which is a packed data rearrangement control indexes generation instruction, and wherein storing the result comprises storing the at least four consecutive non-negative integers in the numerical order as at least four corresponding packed data rearrangement control indexes.

3. The method of claim 1 , wherein storing the consecutive non-negative integers in the numerical order is fixed by the opcode of the instruction.

4. The method of claim 1 , wherein receiving comprises receiving the instruction indicating a rotation amount, and wherein storing the result includes storing a rotated sequence of the at least four consecutive non-negative integers that has been rotated by the rotation amount.

5. The method of claim 1 , wherein storing comprises storing the result which includes the sequence of at least eight consecutive non-negative integers in the numerical order.

6. The method of claim 5 , wherein storing comprises storing the result which includes the sequence of at least thirty-two consecutive non-negative integers in the numerical order.

7. The method of claim 1 , further comprising accessing a sequence of at least four consecutive non-negative integers from a non-architecturally visible storage location that is on-die with an execution unit that is executing the instruction.

8. The method of claim 1 , further comprising:
receiving a second instruction indicating the result, indicating a constant integer stride, and indicating a second destination packed data register; and
storing a second result in the second destination packed data register in response to the second instruction, the second result including a sequence of at least four non-negative integers in numerical order with all consecutive integers of the second result differing by the constant integer stride.

9. An apparatus comprising:
a destination packed data register; and
an execution unit coupled with the destination packed data register, the execution unit, in response to an instruction, which is to indicate the destination packed data register, and is to indicate a register that is to store an offset, but is not to have an immediate, to store a result in the destination packed data register, the result to include a sequence of at least four non-negative integers in numerical order, in which a lowest order one of the at least four non-negative integers is to differ from zero by the offset,
wherein the execution unit is to store the result in response to the instruction that is not to indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location,
wherein an opcode of the instruction is to fix that the execution unit is to store integers in numerical order in the result, and
wherein the instruction does not indicate a memory location.

10. The apparatus of claim 9 , wherein the instruction comprises a packed data rearrangement control indexes generation instruction, and wherein the execution unit, in response to the packed data rearrangement control indexes generation instruction, is to store the sequence of the at least four non-negative integers in the numerical order as at least four corresponding packed data rearrangement control indexes.

11. The apparatus of claim 9 , wherein the opcode of the instruction fixes that the execution unit is to store consecutive non-negative integers in numerical order.

12. The apparatus of claim 9 , wherein the sequence of the at least four non-negative integers is a sequence of the at least four consecutive non-negative integers, and wherein a smallest one of the at least four consecutive non-negative integers is to differ from zero by the integer offset.

13. The apparatus of claim 9 , wherein the instruction is to indicate an integer rotation amount, and wherein the execution unit, in response to the instruction, is to store a rotated sequence of the at least four non-negative integers that is to have been rotated by the integer rotation amount.

14. The apparatus of claim 9 , wherein the execution unit, in response to the instruction, is to store the result which is to include the sequence of at least eight consecutive non-negative integers in the numerical order.

15. The apparatus of claim 9 , wherein the execution unit, in response to the instruction, is to store the result which is to include the sequence of at least thirty-two non-negative integers in the numerical order.

16. The apparatus of claim 9 , further comprising a non-architecturally visible storage location on-die with the execution unit storing a first sequence of at least four consecutive non-negative integers, and wherein the execution unit, in response to the instruction, is to access the first sequence of the at least four consecutive non-negative integers from the non-architecturally visible storage location.

17. A system comprising:
an interconnect;
a processor coupled with the interconnect, the processor including a destination register, the processor, in response to an instruction which is to indicate the destination register, and is to indicate a register that is to provide an offset, but is not to have an immediate, to store a result in the destination register, the result to include a sequence of at least four consecutive non-negative integers in numerical order, in which a lowest order one of the at least four consecutive non-negative integers is to differ from zero by the offset, wherein the processor is to store the result which is to include the sequence of the at least four consecutive non-negative integers in the numerical order without calculating values of the at least four consecutive non-negative integers from a result of a preceding instruction, wherein an opcode of the instruction is to fix that an execution unit is to store integers in numerical order in the result and it is to be implicit to the opcode that the integers in the numerical order are to be stored in the result, and wherein the instruction does not indicate a memory location; and
a dynamic random access memory (DRAM) coupled with the interconnect.

18. The system of claim 17 , wherein a smallest one of the at least four consecutive non-negative integers that is to differ from zero by the integer offset.

19. An article of manufacture comprising:
a non-transitory machine-readable storage medium including one or more solid storage materials, the non-transitory machine-readable storage medium storing instructions including an instruction,
the instruction to indicate a destination packed data register, to indicate a register that is to store an offset, and the instruction not to have an imm

Assignees

• Abraham Seth
• Valentine Robert
• Ould Ahmed Vall Elmoustapha
• Sperber Zeev
• Gradstein Amit
• Intel Corp

Inventors

• Abraham Seth
• Valentine Robert
• Ould-Ahmed-Vall Elmoustapha
• Sperber Zeev
• Gradstein Amit

Classifications

• G06F9/3455

  using stride · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title

• G06F17/10 Primary

  Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title