Non-volatile memory device and controlling apparatus, having extension activating and control parts, where memory device can be operated in an optimum operation mode

Patent metadata

Field	Value
Publication number	US-10565137-B2
Application number	US-50189409-A
Country	US
Kind code	B2
Filing date	Jul 13, 2009
Priority date	Jul 15, 2008
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A memory device controlling apparatus of the present invention includes a device information requesting part that requests device information with respect to a memory device, when recognizing that the memory device is connected to the memory device controlling apparatus, and an extension activating part that activates an extension of the memory device based on the device information acquired in the device information requesting part. The memory device controlling apparatus accesses the memory device using the extension in the memory device. Such a configuration enables the memory device and the memory device controlling apparatus to be operated in an optimum operation mode in accordance with the characteristics of each bus, a host PC, and the memory device.

First claim

What is claimed is:

1. A memory device controlling apparatus enabling a memory device having a plurality of memory modules to be detachable therefrom, the memory device controlling apparatus comprising:
a device information requesting part that receives device information including a striping configuration from the memory device, when recognizing that the memory device is connected to the memory device controlling apparatus;
an extension activating part that activates an extension of the memory device based on the device information acquired in the device information requesting part;
a region determining part that determines a region where a data has been transferred from the memory device to the memory device controlling apparatus based on a striping basis of the striping configuration;
a region counter that manages the data transferred from the memory device to the memory device controlling apparatus on the striping basis of the striping configuration; and
an internal buffer,
wherein the memory device controlling apparatus accesses the memory device using the extension selected based at least on an operable maximum frequency of a clock, a data size, and a maximum data bus width in the memory device, and
wherein the striping configuration includes an information of an order of a plurality of data units that are segmented from the data and an address information of the data stored within the region of a plurality of memory modules of the memory device, and the striping size is a size of each of the data units,
wherein the region determining part is configured to determine a region where the data has been transferred to the memory device controlling apparatus of one of a data unit previously stored in each of regions of each of the memory modules, and the region counter configured to manage the transferred data on the striping basis by setting up one or more flags representing a completion of transfer of the data unit,
wherein each of the plurality of memory modules is non-volatile memory,
wherein the memory device controlling apparatus is configured to receive the plurality of data units from the plurality of memory modules out of order, and
wherein the memory device controlling apparatus manages the internal buffer based on a striping size of the striping configuration by using the region determining part and the region counter, and transfers the data from the memory device controlling apparatus to a host appliance.

2. The memory device controlling apparatus according to claim 1 , wherein the memory device controlling apparatus is capable of being connected to the host appliance, and
when a direct memory access (DMA) transfer from the memory device to the memory device controlling apparatus is performed, a transfer from the memory device controlling apparatus to the host appliance starts at a time when a transfer of a predetermined striping unit from the memory device is completed.

Assignees

• Yamashita Hideaki
• Ootsuka Takeshi
• Panasonic Ip Man Co Ltd

Inventors

• Yamashita Hideaki
• Ootsuka Takeshi

Classifications

• G06F13/1694 Primary

  Configuration of memory controller to different memory types · CPC title