Compute node security

Patent metadata

Field	Value
Publication number	US-10565129-B2
Application number	US-201715637685-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	May 26, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.

First claim

The invention claimed is:

1. A compute node comprising:
at least one cache which implements a hardware transactional memory;
a memory in communication with the at least one cache, the memory storing information associated with a victim process, the information comprising at least one of code and data; and
a processor that loads the information from the memory into the at least one cache and
executes the victim process as transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until the execution of the victim process either aborts or completes, wherein the processor separates sequentially accessed read cache lines of the cache by a page boundary from write cache lines and provides safety margins between read and write cache lines on the same page.

2. The compute node of claim 1 wherein the hardware transactional memory is configured to abort the transactions if at least part of the information is evicted from the cache.

3. The compute node of claim 1 wherein the cache is shared by the victim process and another process which is an attacker process seeking to infer the information through a cache-based side-channel attack.

4. The compute node of claim 1 wherein the cache writes back a result of the victim process to the memory on completion of the execution.

5. The compute node of claim 1 wherein the processor loads the information from the memory into the cache in an oblivious manner.

6. The compute node of claim 1 wherein the processor is instructed to load the information from the memory into the cache by instructions added to the victim process.

7. The compute node of claim 6 wherein the processor is instructed to load the information from the memory into the cache by taking into account a size of a working set.

8. The compute node of claim 1 wherein the processor loads the information from the memory into a read set and a write set of the cache.

9. The compute node of claim 1 wherein the information comprises data and wherein the processor loads the data into a write set of the cache.

10. The compute node of claim 1 wherein the information comprises code and wherein the processor loads the code into a read set of the cache.

11. The compute node of claim 1 wherein the information comprises code and wherein the processor is instructed by instructions added to the victim process to restrict the amount of code in individual ones of the transactions to the size of a first level of the cache and to load the restricted amount of code into the first level cache via execution of the instructions added to the victim process.

12. The compute node of claim 1 wherein the processor is instructed by instructions added to the victim process to reserve a plurality of cache sets in the cache for a write set of the hardware transactional memory.

13. The compute node of claim 1 wherein the victim process comprises instructions added by a compiler which do not change the behavior of the victim process but which enables a cache line to be loaded into an instruction cache without side effects.

14. The compute node of claim 1 comprising an enclave and an untrusted operating system, and wherein the victim process is executed in the enclave and an attacker process is executed by the processor outside the enclave and wherein the victim thread requests, from the untrusted operating system, control over threads running on the processor, and wherein the victim process checks that the untrusted operating system correctly completes the request.

15. The compute node of claim 14 which is a secure processing unit comprising an enclave in an isolated execution environment.

16. A compute node comprising:
at least one cache which implements a hardware transactional memory;
a memory in communication with the at least one cache, the memory storing information associated with a victim process, the information comprising at least one of code and data;
a processor that loads the information from the memory into the at least one cache and
executes the victim process as transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the transactions abort if any of the information is evicted from the cache; and
an enclave that executes a thread and writes a marker to an associated state save area in the enclave when the thread is interrupted and leaves the enclave,
wherein the victim process inspects markers written by the enclave to ensure that the thread has not been interrupted and migrated outside the enclave.

17. A computer-implemented method at a compute node, the method comprising:
implementing a hardware transactional memory at a cache of the compute node;
at a memory in communication with the at least one cache, storing information associated with a victim process, the information comprising code and data;
loading the information, from whole regions of the memory into the at least one cache; and
executing the victim process as transactions using the hardware transactional memory and at least the loaded information so as to ensure that the loaded information remains in the cache until the execution of the victim process either aborts or completes, wherein sequentially accessed read cache lines of the cache are separated by a page boundary from write cache lines and safety margins are provided between read and write cache lines on the same page.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Schuster Felix
• Ohrimenko Olga
• Haller Istvan
• Costa Manuel Silverio Da Silva
• Gruss Daniel
• Lettner Julian

Classifications

• G06F2212/452

  Instruction code · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/1441

  for a range · CPC title

• G06F21/74

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

• G06F21/53

  by executing in a restricted environment, e.g. sandbox or secure virtual machine · CPC title