Device for supervising and initializing ports

Patent metadata

Field	Value
Publication number	US-10565076-B2
Application number	US-201815974784-A
Country	US
Kind code	B2
Filing date	May 9, 2018
Priority date	May 16, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A device for supervising ports of an integrated circuit is arranged for exchanging information with a central processing unit of an integrated circuit and for communicating with ports of the integrated circuit. The device comprises address decoding means, access control means, and parity controlling means. The device for supervising ports comprises read-back information means arranged for receiving input from the port and for passing that input to the parity control means and in that the address decoding means, the access control means, the read-back information means and the parity controlling means are arranged to be operative in a background loop wherein a range of port addresses is monitored. The read-back information means reads data and one or more parity bits stored on ports with an address in the range and the parity controlling means performs a parity check on the one or more parity bits stored on the ports.

First claim

The invention claimed is:

1. Device for supervising ports of an integrated circuit, said device being arranged for exchanging information with a central processing unit of an integrated circuit and for communicating with ports of said integrated circuit and comprising:
address decoding means for decoding an address of a port from which a read operation or to which a write operation is to be performed in accordance with information exchanged with said central processing unit,
access control means arranged for generating a request towards said port to perform said read operation from or said write operation to said port and for receiving a response to said request from said port, said access control means further arranged for performing said write operation to said port,
parity controlling means arranged for performing a parity check on one or more parity bits contained in said information exchanged with said central processing unit and generating an error signal in case said parity check yields no match and arranged for, upon a positive response to said request, generating one or more parity bits when performing said write operation to said port, and carrying out a parity check when performing said read operation from said port and generating an error signal in case said parity check yields no match,
wherein said device for supervising ports comprises read-back information means arranged for receiving input from said port and for passing said input to said parity control means and in that said address decoding means, said access control means, said read-back information means and said parity controlling means are arranged to be operative in a background loop wherein a range of port addresses is monitored and wherein said read-back information means reads data and one or more parity bits stored on ports with an address in said range and said parity controlling means performs a parity check on said one or more parity bits stored on said ports.

2. Device for supervising ports as in claim 1 , wherein said access control means is arranged for interrupting said background loop when an information exchange is requested by said central processing unit.

3. Device for supervising ports as in claim 2 , wherein said access control means is arranged for giving priority to finalising an already started parity check in said background loop when said information exchange is requested by said central processing unit.

4. Device for supervising ports as in claim 3 , wherein said read-back information means is arranged for performing, after completion of said write operation, a read operation on data and parity bits written to said port in said write operation and said parity control means is arranged for performing said parity check.

5. Device for supervising ports as in claim 3 , comprising an initialisation means for initializing one or more ports in a synchronous way with a predefined sequence during an initialization stage.

6. Device for supervising ports as in claim 5 , wherein said parity controlling means is arranged for inverting one or more parity bits comprised in a port initialisation signal before passing the one or more parity bits to said port.

7. Device for supervising ports as in claim 5 , wherein said port is arranged for receiving the port initialization signal and inverting one or more parity bits.

8. Device for supervising ports as in claim 2 , wherein said parity controlling means is arranged for performing a data integrity check on said information received from said central processing unit.

9. Device for supervising ports as in claim 1 , arranged for handling read and write operations with byte precision.

10. Device for supervising ports as in claim 1 , arranged for handling read and write operations with double byte precision.

11. Device for supervising ports as in claim 10 , arranged for handling read and write operations with bit precision.

12. Device for supervising ports as in claim 10 , wherein said access control means is arranged to detect if said port comprises storage means for storing said one or more parity bits and, if so, to include said port's address in said range of port addresses.

13. Integrated circuit comprising a device for supervising ports as in claim 1 .

Assignees

• Melexis Technologies Nv

Inventors

• Heroux Benoit
• Laugier Philippe
• Freitag Thomas

Classifications

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• H03M13/098

  using single parity bit · CPC title

• G06F13/122

  where hardware performs an I/O function other than control of data transfer · CPC title

• G06F11/2221 Primary

  to test input/output devices or peripheral units · CPC title

• G06F11/1032 Primary

  Simple parity · CPC title