Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines

Patent metadata

Field	Value
Publication number	US-10564975-B2
Application number	US-201815884280-A
Country	US
Kind code	B2
Filing date	Jan 30, 2018
Priority date	Mar 25, 2011
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A global front end scheduler to schedule instruction sequences to a plurality of virtual cores implemented via a plurality of partitionable engines. The global front end scheduler includes a thread allocation array to store a set of allocation thread pointers to point to a set of buckets in a bucket buffer in which execution blocks for respective threads are placed, a bucket buffer to provide a matrix of buckets, the bucket buffer including storage for the execution blocks, and a bucket retirement array to store a set of retirement thread pointers that track a next execution block to retire for a thread.

First claim

What is claimed is:

1. A method of a scheduler of a global front end schedule for scheduling instructions to a plurality of virtual cores of a processor, the method comprising:
fetching a thread and block of instructions to schedule;
generating a thread and bucket inheritance vector for the thread and block of instructions, the thread and bucket inheritance vector to track a set of registers that the block of instructions write into; and
forwarding the thread and bucket inheritance vector to one of the plurality of virtual cores for processing.

2. The method of claim 1 , wherein fetching the thread and block of instructions to schedule loads a header of the thread and a header of the block of instructions to generate the thread and bucket inheritance vector without loading the instructions in the block of instructions.

3. The method of claim 1 , further comprising:
loading instructions of the block of instructions at a local front end scheduler of the one of the plurality of virtual cores.

4. The method of claim 1 , wherein the thread and block of instructions to schedule includes a header with a bit vector of destination registers for the block of instructions.

5. The method of claim 1 , further comprising
allocating a new thread to a virtual core; and
updating the inheritance vector for the new thread.

6. The method of claim 5 , wherein updating the inheritance vector changes fields written to by the new thread and does not alter fields the new thread does not write to.

7. The method of claim 1 , further comprising:
determining a control path change by a global branch predictor; and
adding branching destinations in a header for the thread and block of instructions.

8. A system for processing blocks of instructions, the system comprising:
a set of processing resources that are partitionable into a set of virtual cores; and
a processing pipeline coupled to the set of processing resources, the processing pipeline including a global front end scheduler to fetch a thread and block of instructions to schedule, to generate a thread and bucket inheritance vector for the thread and block of instructions, the thread and bucket inheritance vector to track a set of registers that the block of instructions write into, and to forward the thread and bucket inheritance vector to one of the set of virtual cores for processing.

9. The system of claim 8 , wherein the global front end scheduler is further to fetch a header of the thread and block of instructions to schedule to generate the thread and bucket inheritance vector without loading the instructions in the block of instructions.

10. The system of claim 8 , wherein the set of processing resources are to load instructions of the block of instructions at a local front end scheduler of the one of the set of virtual cores.

11. The system of claim 8 , wherein the thread and block of instructions to schedule includes a header with a bit vector of destination registers for the block of instructions.

12. The system of claim 8 , wherein the global front end scheduler is to allocate a new thread to a virtual core, and update the inheritance vector for the new thread.

13. The system of claim 12 , wherein updating the inheritance vector changes fields written to by the new thread and does not alter fields the new thread does not write to.

14. The system of claim 12 , wherein the global front end scheduler further comprises:
a global branch predictor to determine a control path change, and to add branching destinations in a header for the thread and block of instructions.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/30141

  Implementation provisions of register files, e.g. ports · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title