Packed data operation mask shift processors, methods, systems, and instructions

Patent metadata

Field	Value
Publication number	US-10564966-B2
Application number	US-201113977171-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A method of an aspect includes receiving a packed data operation mask shift instruction. The packed data operation mask shift instruction indicates a source having a packed data operation mask, indicates a shift count number of bits, and indicates a destination. The method further includes storing a result in the destination in response to the packed data operation mask shift instruction. The result includes a sequence of bits of the packed data operation mask that have been shifted by the shift count number of bits. Other methods, apparatus, systems, and instructions are disclosed.

First claim

What is claimed is:

1. A method comprising:
receiving a packed data operation mask shift instruction of an instruction set of a processor, the packed data operation mask shift instruction indicating a source packed data operation mask register having a packed data operation mask, indicating a shift count number of bits, and indicating a destination packed data operation mask register, wherein the source and destination packed data operation mask registers are among a plurality of packed data operation mask registers that are not general-purpose registers, wherein the source packed data operation mask register supports both merging masking and zeroing masking, and wherein a given packed data operation mask register of the plurality of packed data operation mask registers is not able to be used for predication but all other of the plurality of packed data operation mask registers are able to be used for the predication and support the merging masking and the zeroing masking;
generating a result with an execution unit including shift circuitry in response to the packed data operation mask shift instruction by shifting the packed data operation mask with the shift circuitry;
storing the result in the destination packed data operation mask register in response to the packed data operation mask shift instruction, the result including a sequence of bits of the packed data operation mask that have been shifted by the shift count number of bits.

2. The method of claim 1 , wherein storing the result comprises storing the sequence of the bits of the packed data operation mask that have been logically shifted to the right by the shift count number of bits with a number of zeros shifted in on the left equal to the shift count number of bits.

3. The method of claim 1 , wherein storing the result comprises storing the sequence of the bits of the packed data operation mask that have been logically shifted to the left by the shift count number of bits with a number of zeros shifted in on the right equal to the shift count number of bits.

4. The method of claim 1 , wherein the packed data operation mask is an N-bit packed data operation mask, wherein the shift count number of bits is an M-bit shift count number of bits, and wherein the result includes:
(a) in a least significant N-bits of the destination packed data operation mask register, an (N-M)-bit sequence of the bits of the N-bit packed data operation mask that has been shifted by the M-bit shift count number of bits, and M-bits that all have a same bit value; and
(b) in a most significant remainder of the destination packed data operation mask register a plurality of bits that all have a value of zero.

5. The method of claim 4 , wherein the (N-M)-bit sequence of the bits has been logically shifted by the M-bit shift count number of bits, and wherein the M-bits all have a value of zero.

6. The method of claim 4 , wherein the N-bit packed data operation mask is a 16-bit packed data operation mask, and wherein the destination packed data operation mask register includes more than 16-bits.

7. The method of claim 1 , further comprising receiving a masked packed data instruction indicating the result as a predicate operand.

8. An apparatus comprising:
a plurality of general-purpose registers;
a plurality of packed data operation mask registers, including a packed data operation mask register to store a packed data operation mask, wherein the packed data operation mask register is not a general-purpose register, and wherein all but one of the plurality of packed data operation mask registers, including the packed data operation mask register, can be used for predication and support both merging masking and zeroing masking;
a decode unit to decode a packed data operation mask shift instruction; and
an execution unit coupled with the packed data operation mask register, the execution unit including shift circuitry, the execution unit, in response to the decode of the packed data operation mask shift instruction that is to indicate the packed data operation mask register as a source, that is to indicate a shift count number of bits, and that is to indicate a destination, to:
shift the packed data operation mask with the shift circuitry as part of generation of a result; and
store the result in the destination, the result to include a sequence of bits of the packed data operation mask that are to have been shifted by the execution unit by the shift count number of bits.

9. The apparatus of claim 8 , wherein the execution unit is in response to the packed data operation mask shift instruction to store a result that is to include the sequence of the bits of the packed data operation mask that are to have been logically shifted to the right by the shift count number of bits with a number of zeros shifted in on the left equal to the shift count number of bits.

10. The apparatus of claim 8 , wherein the execution unit is, in response to the packed data operation mask shift instruction, to store a result that is to include the sequence of the bits of the packed data operation mask that are to have been logically shifted to the left by the shift count number of bits with a number of zeros shifted in on the right equal to the shift count number of bits.

11. The apparatus of claim 8 , wherein the packed data operation mask is an N-bit packed data operation mask, wherein the shift count number of bits is an M-bit shift count number of bits, and wherein the execution unit is, in response to the packed data operation mask shift instruction, to store a result that is to include:
(a) in a least significant N-bits of the destination, an (N-M)-bit sequence of the bits of the N-bit packed data operation mask that is to have been shifted by the M-bit shift count number of bits, and M-bits that all are to have a same bit value; and
(b) in a most significant remainder of the destination a plurality of bits that all are to have a value of zero.

12. The apparatus of claim 11 , wherein the execution unit is to store the (N-M)-bit sequence of the bits that is to have been logically shifted by the M-bit shift count number of bits, and the M-bits that all are to have a value of zero.

13. The apparatus of claim 11 , wherein the N-bit packed data operation mask is an 8-bit packed data operation mask, and wherein the destination is a packed data operation mask register that is to include more than 8-bits.

14. The apparatus of claim 11 , wherein the N-bit packed data operation mask is a 32-bit packed data operation mask, and wherein the destination is a packed data operation mask register that is to include more than 32-bits.

15. The apparatus of claim 8 , wherein the packed data operation mask shift instruction is to explicitly specify the packed data operation mask register, is to explicitly specify the destination, and is to specify the shift count number of bits in an immediate.

16. A system comprising:
an interconnect;
a processor coupled with the interconnect, the processor including a plurality of general-purpose registers, and a plurality of packed data operation mask registers, including a packed data operation mask register to store a packed data operation mask, wherein the packed data operation mask register is not a general-purpose register, wherein all but one of the plurality of packed data operation mask registers, including the packed data operation mask register, can be used for predication and support both merging masking and zeroing masking, the processor including shift circuitry, the processor, in response to a packed data operation mask shift instruction of an instruction

Assignees

• Toll Bret L
• Valentine Robert
• Corbal San Adrian Jesus
• Ould Ahmed Vall Elmoustapha
• Charney Mark J
• Intel Corp

Inventors

• Toll Bret L
• Valentine Robert
• Corbal San Adrian Jesus
• Ould-Ahmed Vall Elmoustapha
• Charney Mark J

Classifications

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title