Array substrate, its driving method and manufacturing method, and display device

Patent metadata

Field	Value
Publication number	US-10564772-B2
Application number	US-201615233408-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Jan 14, 2016
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.

First claim

What is claimed is:

1. An array substrate, comprising:
a transistor layer arranged on a base;
a first transparent conductive layer;
a first insulation layer;
a second transparent conductive layer;
a second insulation layer; and
a third transparent conductive layer,

wherein:
the first transparent conductive layer, the first insulation layer, the second transparent conductive layer, the second insulation layer, and the third transparent conductive layer are arranged sequentially, in that order, on the transistor layer,
the first transparent conductive layer covers the transistor layer at a display area, the first transparent conductive layer is configured to be a first common electrode at a display stage by applying a common voltage to the first transparent conductive layer at the display stage, and configured to be a shielding layer at a touch stage, the second transparent conductive layer comprises a pattern of touch electrodes, the second transparent conductive layer is in direct physical contact with the second insulation layer and the first insulation layer, the touch electrodes are configured to be a second common electrode of the array substrate at the display stage by applying the common voltage to the touch electrodes at the display stage, and the third transparent conductive layer comprises a pattern of pixel electrodes; and
within any one of pixel areas of the display area,
a corresponding pixel electrode is connected to a pixel electrode connection end on a source-drain metal layer of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the via-hole is arranged between a pattern of the corresponding pixel electrode and the source-drain metal layer,
a passivation layer of the transistor layer is provided with a second opening so as to expose a portion of the source-drain metal layer, thereby to form the pixel electrode connection end,
the first transparent conductive layer is provided with a first opening at a position corresponding to the via-hole.

2. The array substrate according to claim 1 , wherein within any one of the pixel areas of the display area, the pixel electrode overlaps the first transparent conductive layer to form a first storage capacitor at the pixel area, and the pixel electrode overlaps a corresponding touch electrode to form a second storage capacitor at the pixel area.

3. The array substrate according to claim 1 , wherein
the transistor layer comprises an active layer, a gate insulation layer, a gate metal layer, an interlayer medium layer, the source-drain metal layer and the passivation layer formed seguentially.

4. The array substrate according to claim 1 , wherein the first transparent conductive layer and the second transparent conductive layer are each arranged at an area outside an area of the via-hole, and separated from the via-hole.

5. The array substrate according to claim 3 , wherein the gate insulation layer and the interlayer medium layer are provided with another via-hole through which the source-drain metal layer is connected to the active layer.

6. The array substrate according to claim 1 , wherein the first transparent conductive layer, the first insulation layer, the second transparent conductive layer, the second insulation layer and the third transparent conductive layer are each of a thickness within a range from 100 Å to 5000 Å.

7. A display device, comprising the array substrate according to claim 1 .

8. The display device according to claim 7 , wherein within any one of pixel areas of the display area, the pixel electrode overlaps the first transparent conductive layer to form a first storage capacitor at the pixel area, and the pixel electrode overlaps a corresponding touch electrode to form a second storage capacitor at the pixel area.

9. The display device according to claim 7 , wherein
the transistor layer comprises an active layer, a gate insulation layer, a gate metal layer, an interlayer medium layer, the source-drain metal layer and the passivation layer formed sequentially.

10. A method for driving an array substrate, wherein the array substrate comprises:
a transistor layer arranged on a base;
a first transparent conductive layer;
a first insulation layer;
a second transparent conductive layer;
a second insulation layer; and
a third transparent conductive layer, wherein:
the first transparent conductive layer, the first insulation layer, the second transparent conductive layer, the second insulation layer, and the third transparent conductive layer are arranged sequentially, in that order, on the transistor layer,
the first transparent conductive layer covers the transistor layer at a display area, the first transparent conductive layer is configured to be a first common electrode at a display stage by applying a common voltage to the first transparent conductive layer at the display stage, and configured to be a shielding layer at a touch stage, the second transparent conductive layer comprises a pattern of touch electrodes, the second transparent conductive layer is in direct physical contact with the second insulation layer and the first insulation layer, the touch electrodes are configured to be a second common electrode of the array substrate at the display stage by applying the common voltage to the touch electrodes at the display stage, and the third transparent conductive layer comprises a pattern of pixel electrodes; and
within any one of pixel areas of the display area,
a corresponding pixel electrode is connected to a pixel electrode connection end on a source-drain metal layer of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the via-hole is arranged between a pattern of the corresponding pixel electrode and the source-drain metal layer,
a passivation layer of the transistor layer is provided with a second opening so as to expose a portion of the source-drain metal layer, thereby to form the pixel electrode connection end,
the first transparent conductive layer is provided with a first opening at a position corresponding to the via-hole, the method comprising the steps of:
at the display stage, applying the common voltage to the touch electrode in the second transparent conductive layer and to the first transparent conductive layer; and
at the touch stage, applying a touch voltage signal to the touch electrode in the second transparent conductive layer, or receiving a touch sensing signal from the touch electrode in the second transparent conductive layer,
wherein the display stage is temporally separated from the touch stage within each image frame.

11. The method according to claim 10 , further comprising:
at the touch stage, applying the common voltage to the first transparent conductive layer.

12. The method according to claim 10 , further comprising:
at the touch stage, setting pixel electrodes in the third transparent conductive layer to be in a floating state.

13. The method according to claim 10 , wherein the common voltage is of a value within a range from −5V to +5V.

14. A method for manufacturing an array substrate, comprising steps of:
forming a transistor layer on a base of the array substrate;
forming a first transparent conductive layer covering the transistor layer at a display area, and the first transparent conductive layer being provided with a first opening at a position corresponding to a via-hole for connecting a pixel electrode connection end of the transistor layer;
forming a first insulation layer covering the first transparent conductive layer, the first transparent con

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Sun Chaochao
• Liu Huafeng
• Zhao Shengwei
• Zhang Kai
• Yang Lei
• Ye Lulu
• Lv Jingping
• Wang Chao
• Hu Chongliang
• Yang Meng
• Ding Duolong
• Shun Bule
• Xie Lin
• Li Yao
• Sun Shimin

Classifications

• G06F2203/04107

  Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G02F1/13338

  Input devices, e.g. touch panels · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G09G3/3659

  the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes · CPC title