Method to optimize core count for concurrent single and multi-thread application performance

Patent metadata

Field	Value
Publication number	US-10564702-B2
Application number	US-201715636021-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Jun 28, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A system, method, and computer-readable medium are disclosed for performing a core optimization operation, comprising: enabling all of a plurality of processor cores of a processor; selectively turning off at least one of the plurality of processor cores, the selectively turning off the at least one of the plurality of processor cores being based upon an application to be executed by the processor, the selectively turning off being performed dynamically during runtime of the processor; and, controlling process thread distribution to the plurality of processor cores via an operating system executing on the processor, the process thread distribution not distributing threads to the turned off at least one of the plurality of processor cores.

First claim

What is claimed is:

1. A computer-implementable method for performing a core optimization operation, comprising:
enabling all of a plurality of processor cores of a processor;
selectively turning off at least one of the plurality of processor cores, the selectively turning off the at least one of the plurality of processor cores being based upon an application to be executed by the processor, the selectively turning off being performed dynamically during runtime of the processor; and
controlling process thread distribution to the plurality of processor cores via an operating system executing on the processor, the process thread distribution not distributing threads to the turned off at least one of the plurality of processor cores, the controlling process thread distribution comprising removing a thread and associated memory mapping from a turned off core and redistributing the thread to other available cores;
wherein the core optimization is performed by a core optimization system, the core optimization system comprising:
an operating system scheduler;
a core mask filter that stores information regarding which cores should be used for particular applications; and
a core mask and affinity module, wherein the core mask and affinity module:
comprises a bit mask indicating cores on which the thread should run; and
restricts execution of the thread from the turned off core to a particular one or more cores from the other available cores based on a determination of whether an application policy associated with the thread from the turned off core indicates hyper-threading is disabled.

2. The method of claim 1 , wherein:
the operating system defaults to honor a process thread distribution setting by not using the turned off at least one of the plurality of processor cores.

3. The method of claim 1 , further comprising:
turning on the turned off at least one of the plurality of processor cores at runtime, thereby resulting in a mixed mode enablement of the plurality of processor cores.

4. The method of claim 1 , further comprising:
restricting schedule of threads onto a particular core when hyper-threading is disabled via a core affinity management operation.

5. The method of claim 4 , wherein:
the core affinity management operation removes the thread and associated memory mapping from a particular core and redistributes the thread to other available cores.

6. The method of claim 5 , wherein:
removing the thread and associated memory causes the particular core to naturally transition to a sleep state.

7. A system comprising:
a processor;
a data bus coupled to the processor; and
a non-transitory, computer-readable storage medium embodying computer program code, the non-transitory, computer-readable storage medium being coupled to the data bus, the computer program code interacting with a plurality of computer operations and comprising instructions executable by the processor and configured for:
enabling all of a plurality of processor cores of a processor;
selectively turning off at least one of the plurality of processor cores, the selectively turning off the at least one of the plurality of processor cores being based upon an application to be executed by the processor, the selectively turning off being performed dynamically during runtime of the processor; and
controlling process thread distribution to the plurality of processor cores via an operating system executing on the processor, the process thread distribution not distributing threads to the turned off at least one of the plurality of processor cores, the controlling process thread distribution comprising removing a thread and associated memory mapping from a turned off core, and redistributing the thread to other available cores;
wherein the core optimization is performed by a core optimization system, the core optimization system comprising:
an operating system scheduler;
a core mask filter that stores information regarding which cores should be used for particular applications; and
a core mask and affinity module, wherein the core mask and affinity module:
comprises a bit mask indicating which cores on which the thread should run; and
restricts execution of the thread from the turned off core to a particular one or more cores from the other available cores based on a determination of whether an application policy associated with the thread from the turned off core indicates hyper-threading is disabled.

8. The system of claim 7 , wherein:
the operating system defaults to honor a process thread distribution setting by not using the turned off at least one of the plurality of processor cores.

9. The system of claim 7 , wherein the instructions executable by the processor are further configured for:
turning on the turned off at least one of the plurality of processor cores at runtime, thereby resulting in a mixed mode enablement of the plurality of processor cores.

10. The system of claim 7 , wherein the instructions executable by the processor are further configured for:
restricting schedule of threads onto a particular core when hyper-threading is disabled via a core affinity management operation.

11. The system of claim 10 , wherein:
the core affinity management operation removes a thread and associated memory mapping from a particular core and redistributes the thread to other available cores.

12. The system of claim 11 , wherein:
removing the thread and associated memory causes the particular core to naturally transition to a sleep state.

13. A non-transitory, computer-readable storage medium embodying computer program code, the computer program code comprising computer executable instructions configured for:
enabling all of a plurality of processor cores of a processor;
selectively turning off at least one of the plurality of processor cores, the selectively turning off the at least one of the plurality of processor cores being based upon an application to be executed by the processor, the selectively turning off being performed dynamically during runtime of the processor; and
controlling process thread distribution to the plurality of processor cores via an operating system executing on the processor, the process thread distribution not distributing threads to the turned off at least one of the plurality of processor cores, the controlling process thread distribution comprising removing a thread and associated memory mapping from a turned off core and redistributing the thread to other available cores,
wherein the core optimization is performed by a core optimization system, the core optimization system comprising:
an operating system scheduler;
a core mask filter that stores information regarding which cores should be used for particular applications; and
a core mask and affinity module, wherein the core mask and affinity module:
comprises a bit mask indicating which cores on which the thread should run; and
restricts execution of the thread from the turned off core to a particular one or more cores from the other available cores based on a determination of whether an application policy associated with the thread from the turned off core indicates hyper-threading is disabled.

14. The non-transitory, computer-readable storage medium of claim 13 , wherein:
the operating system defaults to honor a process thread distribution setting by not using the turned off at least one of the plurality of processor cores.

15. The non-transitory, computer-readable storage medium of claim 13 , wherein the computer executable instructions are further configured for:
turning on the turned off at least one of

Assignees

• Dell Products Lp

Inventors

• Khosrowpour Farzad
• Markow Mitchell A
• Sexton Steven A

Classifications

• G06F9/4818

  Priority circuits therefor · CPC title

• G06F2209/503

  Resource availability · CPC title

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F2209/5018

  Thread allocation · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title