Diagnostic system for a DC-DC voltage converter

US10564226B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10564226-B2
Application numberUS-201715808967-A
CountryUS
Kind codeB2
Filing dateNov 10, 2017
Priority dateNov 25, 2016
Publication dateFeb 18, 2020
Grant dateFeb 18, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A diagnostic system for a DC-DC voltage converter having a high voltage switch, a low voltage switch, and a DC-DC voltage converter control circuit is provided. The system includes first and second tri-state buffer ICs and a microcontroller. The first tri-state buffer IC receives a first shutdown indicator voltage from the DC-DC voltage converter control circuit indicating that a first plurality of FET switches in a high side FET IC and a second plurality of FET switches in a low side FET IC have been transitioned to an open operational state. The first tri-state buffer IC outputs a second shutdown indicator voltage to the microcontroller that indicates that the first and second plurality of FET switches have been transitioned to the open operational state.

First claim

Opening claim text (preview).

What is claimed is: 1. A diagnostic system for a DC-DC voltage converter, comprising: the DC-DC voltage converter having a high voltage switch, a low voltage switch, a DC-DC voltage converter control circuit, a first electrical node, a second electrical node, a third electrical node, and a fourth electrical node; the high voltage switch being electrically coupled between and to the first and second electrical nodes; the low voltage switch being electrically coupled between and to the third and fourth electrical nodes; the DC-DC voltage converter control circuit being electrically coupled between and to the second and third electrical nodes; the DC-DC voltage converter control circuit having a high side FET IC and a low side FET IC; the high side FET IC having a first plurality of FET switches therein, the low side FET IC having a second plurality of FET switches therein, each FET switch of the first plurality of FET switches being electrically coupled to a respective FET switch of the second plurality of FET switches; a first tri-state buffer IC comprising a first pin, a second pin, a third pin, a fourth pin and a fifth pin; wherein the first pin receives a first shutdown indicator voltage, the second pin outputs a second shutdown indicator voltage, the third pin receives a first control voltage, the fourth pin outputs a second control voltage and the fifth pin is electrically coupled to an electrical ground; a second tri-state buffer IC comprising a first pin, a second pin, a third pin, a fourth pin and a fifth pin; wherein the first pin receives a third shutdown indicator voltage, the second pin outputs a fourth shutdown indicator voltage, the third pin receives a third control voltage, the fourth pin outputs a fourth control voltage and the fifth pin is electrically coupled to an electrical ground; and a microcontroller being electrically coupled to the first and second tri-state buffer ICs; the first tri-state buffer IC receiving the first shutdown indicator voltage at the first pin thereof from the DC-DC voltage converter control circuit indicating that the first plurality of FET switches in the high side FET IC and the second plurality of FET switches in the low side FET IC have been transitioned to an open operational state; the first tri-state buffer IC outputting the second shutdown indicator voltage at the second pin thereof in response to receiving the first shutdown indicator voltage, the second shutdown indicator voltage being received by the microcontroller and indicating that the first and second plurality of FET switches have been transitioned to the open operational state; the second tri-state buffer IC receiving the third shutdown indicator voltage at the first pin thereof from the DC-DC voltage converter control circuit indicating that the first and second plurality of FET switches have been transitioned to the open operational state; the second tri-state buffer IC outputting the fourth shutdown indicator voltage at the second pin thereof in response to receiving the third shutdown indicator voltage, the fourth shutdown indicator voltage being received by the microcontroller and indicating that the first and second plurality of FET switches have been transitioned to the open operational state; and the microcontroller storing a shutdown indicator flag in a memory device indicating that the first and second plurality of FET switches have been transitioned to the open operational state, in response to receiving at least one of the second and fourth shutdown indicator voltages. 2. The diagnostic system for the DC-DC voltage converter of claim 1 , wherein the fourth shutdown indicator voltage is greater than the second shutdown indicator voltage. 3. The diagnostic system for the DC-DC voltage converter of claim 1 , wherein: the microcontroller generating the first control voltage that is received at the third pin of the first tri-state buffer IC for commanding the low voltage switch to be transitioned to the open operational state; the first tri-state buffer IC outputting the second control voltage at the fourth pin thereof in response to receiving the first control voltage, the second control voltage inducing the low voltage switch to transition to the open operational state; the microcontroller generating the third control voltage that is received at the third pin of the second tri-state buffer IC for commanding the high voltage switch to be transitioned to the open operational state; and the second tri-state buffer IC outputting the fourth control voltage at the fourth pin thereof in response to receiving the third control voltage, the fourth control voltage inducing the high voltage switch to transition to the open operational state. 4. The diagnostic system for the DC-DC voltage converter of claim 3 , wherein the fourth control voltage is greater than the second control voltage. 5. A diagnostic system for a DC-DC voltage converter, comprising: the DC-DC voltage converter having a high voltage switch, a low voltage switch, a DC-DC voltage converter control circuit, a first electrical node, a second electrical node, a third electrical node, and a fourth electrical node; the high voltage switch being electrically coupled between and to the first and second electrical nodes; the low voltage switch being electrically coupled between and to the third and fourth electrical nodes; the DC-DC voltage converter control circuit being electrically coupled between and to the second and third electrical nodes; the DC-DC voltage converter control circuit having a high side FET IC and a low side FET IC; the high side FET IC having a first plurality of FET switches therein, the low side FET IC having a second plurality of FET switches therein, each FET switch of the first plurality of FET switches being electrically coupled to a respective FET switch of the second plurality of FET switches; a first tri-state buffer IC comprising a first pin, a second pin, a third pin, a fourth pin and a fifth pin; wherein the first pin receives a first electrical short circuit indicator voltage, the second pin outputs a second electrical short circuit indicator voltage, the third pin receives a first control voltage, the fourth pin outputs a second control voltage and the fifth pin is electrically coupled to electrical ground; a second tri-state buffer IC comprising a first pin, a second pin, a third pin, a fourth pin and a fifth pin; wherein the first pin receives a third electrical short circuit indicator voltage, the second pin outputs a fourth electrical short circuit indicator voltage, the third pin receives a third control voltage, the fourth pin outputs a fourth control voltage and the fifth pin is electrically coupled to an electrical ground; and a microcontroller being electrically coupled to the first and second tri-state buffer ICs; the first tri-state buffer IC receiving the first electrical short circuit indicator voltage at the first pin thereof from the DC-DC voltage converter control circuit indicating that a first FET switch in one of the first plurality of FET switches in the high side FET IC and the second plurality of FET switches in the low side FET IC has a short circuit condition; the first tri-state buffer IC outputting the second electrical short circuit indicator voltage at the second pin thereof in response to receiving the first electrical short circuit indicator voltage, the second electrical short circuit indicator voltage being received by the microcontroller and indicating that the first FET switch has the short circuit condition; the second tri-state buffer IC receiving the third electrical short circuit indicator voltage at the first pin thereof from the DC-DC voltage converter control circuit indicating that the first FET switch has the short circuit condition; the s

Assignees

Inventors

Classifications

  • Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title

  • Modifications for indicating state of switch · CPC title

  • G01R31/40Primary

    Testing power supplies (testing photovoltaic devices H02S50/10) · CPC title

  • Modifications for resetting core switching units to a predetermined state · CPC title

  • Buck-boost converters (H02M3/1584 takes precedence) · CPC title

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What does patent US10564226B2 cover?
A diagnostic system for a DC-DC voltage converter having a high voltage switch, a low voltage switch, and a DC-DC voltage converter control circuit is provided. The system includes first and second tri-state buffer ICs and a microcontroller. The first tri-state buffer IC receives a first shutdown indicator voltage from the DC-DC voltage converter control circuit indicating that a first pluralit…
Who is the assignee on this patent?
Lg Chemical Ltd
What technology area does this patent fall under?
Primary CPC classification G01R31/40. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 18 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).