Processor for enhancing network security

Patent metadata

Field	Value
Publication number	US-10560475-B2
Application number	US-201715729640-A
Country	US
Kind code	B2
Filing date	Oct 10, 2017
Priority date	Mar 7, 2016
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

First claim

What is claimed is:

1. A processor for enhancing network security, comprising an input bus for transferring at least a portion of at least a network packet; a semiconductor substrate with transistors thereon; and, at least one thousand storage-processing units (SPU's) disposed on said semiconductor substrate and communicatively coupled with said input bus, each of said SPU's comprising:
at least a three-dimensional memory (3D-M) array for storing at least a portion of a rule pattern;
a pattern-processing circuit for performing pattern matching or pattern recognition on said network packet against said rule pattern;
a plurality of inter-storage-processor (ISP) connections for communicatively coupling said 3D-M array and said pattern-processing circuit;
wherein said pattern-processing circuit is disposed on said semiconductor substrate; said 3D-M array is stacked above said pattern-processing circuit; and, said processor comprises no more semiconductor substrate other than said semiconductor substrate.

2. The processor according to claim 1 , wherein said pattern-processing circuit includes at least a text-matching circuit or a code-matching circuit.

3. The processor according to claim 1 , wherein said pattern-processing circuit comprises at least a comparator, a content-addressable-memory (CAM), or a finite-state automata (FSA) circuit.

4. The processor according to claim 1 , wherein said 3D-M array is a three-dimensional horizontal memory (3D-M H ) array.

5. The processor according to claim 1 , wherein said 3D-M array is a three-dimensional vertical memory (3D-M V ) array.

6. The processor according to claim 1 , wherein said 3D-M array at least partially covers said pattern-processing circuit.

7. The processor according to claim 1 , wherein said pattern-processing circuit is covered by at least two 3D-M arrays.

8. A processor for enhancing network security, comprising an input bus for transferring at least a portion of at least a network packet; a semiconductor substrate with transistors thereon; and, a plurality of storage-processing units (SPU's) disposed on said semiconductor substrate and communicatively coupled with said input bus, each of said SPU's comprising:
at least a three-dimensional memory (3D-M) array for storing at least a portion of a rule pattern;
a pattern-processing circuit for performing pattern matching or pattern recognition on said network packet against said rule pattern;
at least one thousand contact vias for communicatively coupling said 3D-M array and said pattern-processing circuit;
wherein said pattern-processing circuit is disposed on said semiconductor substrate; said 3D-M array is stacked above said pattern-processing circuit; and, said processor comprises no more semiconductor substrate other than said semiconductor substrate.

9. The processor according to claim 8 , wherein said pattern-processing circuit includes at least a text-matching circuit, and/or a code-matching circuit.

10. The processor according to claim 8 , wherein said pattern-processing circuit comprises at least a comparator, a content-addressable-memory (CAM), or a finite-state automata (FSA) circuit.

11. The processor according to claim 8 , wherein said 3D-M array is a three-dimensional horizontal memory (3D-M H ) array.

12. The processor according to claim 8 , wherein said 3D-M array is a three-dimensional vertical memory (3D-M V ) array.

13. The processor according to claim 8 , wherein said 3D-M array at least partially covers said pattern-processing circuit.

14. The processor according to claim 8 , wherein said pattern-processing circuit is covered by at least two 3D-M arrays.

15. A processor for enhancing network security, comprising an input bus for transferring at least a portion of at least a network packet; a semiconductor substrate with transistors thereon; and, a plurality of storage-processing units (SPU's) disposed on said semiconductor substrate and communicatively coupled with said input bus, each of said SPU's comprising:
at least a three-dimensional memory (3D-M) array for storing at least a portion of a rule pattern;
a pattern-processing circuit for performing pattern matching or pattern recognition on said network packet against said rule pattern;
a plurality of contact vias for communicatively coupling said 3D-M array and said pattern-processing circuit, wherein the length of said contact vias is on the order of a micron;
wherein said pattern-processing circuit is disposed on said semiconductor substrate; said 3D-M array is stacked above said pattern-processing circuit; and, said data storage comprises no more semiconductor substrate other than said semiconductor substrate.

16. The processor according to claim 15 , wherein said pattern-processing circuit includes at least a text-matching circuit, and/or a code-matching circuit.

17. The processor according to claim 15 , wherein said 3D-M array is a three-dimensional horizontal memory (3D-M H ) array.

18. The processor according to claim 15 , wherein said 3D-M array is a three-dimensional vertical memory (3D-M V ) array.

19. The processor according to claim 15 , wherein said 3D-M array at least partially covers said pattern-processing circuit.

20. The processor according to claim 15 , wherein said pattern-processing circuit is covered by at least two 3D-M arrays.

Assignees

• Chengdu Haicun Ip Technology Llc

Inventors

• Zhang Guobiao

Classifications

• G11C17/143

  using laser-fusible links · CPC title

• G11C17/10

  in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C17/14

  in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title