Techniques for data compression

Patent metadata

Field	Value
Publication number	US-10560125-B2
Application number	US-201816037241-A
Country	US
Kind code	B2
Filing date	Jul 17, 2018
Priority date	Jan 26, 2018
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

This disclosure relates to a data processing device, comprising: a digital front end (DFE) configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols; a baseband (BB) circuitry configured to process the digital data in baseband; and a digital interface between the DFE and the BB circuitry, wherein the DFE comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry.

First claim

The invention claimed is:

1. A data processing device, comprising:
a digital front end (DFE) circuitry configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols;
a baseband (BB) circuitry configured to process the digital data in baseband; and
a digital interface between the DFE circuitry and the BB circuitry,
wherein the DFE circuitry comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry,
wherein the data compression circuitry is configured to compress the plurality of data symbols based on a removal of an unused subcarrier and the removal of a cyclic prefix, the data compression circuitry utilizing an OFDM-symbol-aligned Fast Fourier Transform (FFT) window for data compression to substantially eliminate out-of-band spectral content for data transmission.

2. The data processing device of claim 1 ,
wherein the data compression circuitry comprises a Fast Fourier Transform (FFT) circuitry configured to perform a compression of the plurality of data symbols.

3. The data processing device of claim 1 ,
wherein the plurality of data symbols comprises a plurality of Orthogonal Frequency Division Multiplex (OFDM) symbols.

4. The data processing device of claim 1 ,
wherein the digital interface is configured to transmit frequency domain samples of the plurality of data symbols between the DFE circuitry and the BB circuitry.

5. The data processing device of claim 2 ,
wherein the data compression circuitry is configured to compress the plurality of data symbols based on using different word lengths for inband FFT samples and out-of-band FFT samples.

6. The data processing device of claim 1 ,
wherein the data compression circuitry is configured to compress the plurality of data symbols based on lossless compression when the data compression circuitry is operated in a lossless compressor mode.

7. The data processing device of claim 6 ,
wherein the data compression circuitry is configured to compress the plurality of data symbols into OFDM symbol-aligned frequency domain samples when the data compression circuitry is operated in the lossless compressor mode.

8. The data processing device of claim 7 ,
wherein a symbol boundary position of the OFDM symbol-aligned frequency domain samples is known when the data compression circuitry is operated in the lossless compressor mode.

9. The data processing device of claim 1 ,
wherein the data compression circuitry is configured to compress the plurality of data symbols based on lossy compression when the data compression circuitry is operated in a lossy compressor mode.

10. The data processing device of claim 9 ,
wherein the data compression circuitry is configured to compress the plurality of data symbols into non-OFDM symbol-aligned frequency domain samples when the data compression circuitry is operated in the lossy compressor mode.

11. The data processing device of claim 1 , comprising:
control loop processing circuitry arranged between the BB circuitry and the DFE circuitry, wherein the control loop processing circuitry is configured to time-align the compressed data symbols with non-compressed data symbols.

12. The data processing device of claim 11 ,
wherein the control loop processing circuitry is configured to time-align the compressed data symbols in lossless compressor mode with the compressed data symbols in lossy compressor mode.

13. The data processing device of claim 1 , wherein the data compression circuitry is configured to (i) compress the plurality of data symbols into OFDM symbol-aligned frequency domain samples when the data compression circuitry is operated in a lossless compressor mode in accordance with the removal of the unused subcarrier, and (ii) to compress the plurality of data symbols into non-OFDM symbol-aligned frequency domain samples when the data compression circuitry is operated in a lossy compressor mode.

14. The data processing device of claim 2 , wherein the FFT circuitry is configured to compress the plurality of data symbols into non-OFDM symbol-aligned frequency domain samples using frequency-dependent conversion from fixed point into floating point with different word lengths.

15. The data processing device of claim 14 , wherein the BB circuitry includes decompressor circuitry configured to map, in a frequency-dependent manner, data compressed via the data compression circuitry from a floating point format to an input format utilized by inverse Fast Fourier Transform (IFFT) circuitry.

Assignees

• Intel Corp

Inventors

• Talwar Shilpa
• Drewes Christian
• Augustin Andreas
• Noest Peter
• Mueller-Weinfurtner Stefan
• Orhan Oner
• Nikopour Hosein
• Nam Junyoung

Classifications

• H03M7/30

  Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction · CPC title

• H04W28/065

  using assembly or disassembly of packets · CPC title

• H03M7/3059

  Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression · CPC title

• H04L25/03993

  Noise whitening · CPC title

• H04B1/0014 Primary

  using DSP [Digital Signal Processor] quadrature modulation and demodulation · CPC title