Isolation module for use between power rails in an integrated circuit

Patent metadata

Field	Value
Publication number	US-10560094-B2
Application number	US-201715670740-A
Country	US
Kind code	B2
Filing date	Aug 7, 2017
Priority date	Oct 4, 2013
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.

First claim

What is claimed is:

1. A system comprising:
a processor circuit;
a power converter circuit coupled to the processor circuit and configured to provide, to the processor circuit, regulated DC power supply signals including first and second voltage signals;
wherein the processor circuit comprises a semiconductor die, the semiconductor die including first and second power domains configured to receive the first and second voltage signals, respectively, and wherein the processor circuit further comprises a first integrated inductor circuit and a first integrated capacitor circuit;
wherein each of the first and second power domains includes at least one power rail, and wherein each of the power rails is configured to provide different power signals to respective consumer circuits, and
wherein a first power rail in the first power domain is coupled to a second power rail using the first integrated inductor circuit and the first integrated capacitor circuit.

2. The system of claim 1 , wherein the first power domain comprises the first and second power rails.

3. The system of claim 1 , wherein the first integrated inductor circuit comprises multiple stacked planar traces that are electrically coupled in series and that are configured to provide an inductance.

4. The system of claim 3 , wherein multiple ones of the stacked planar traces comprise at least one trace that turns about 90 degrees.

5. The system of claim 1 , wherein the first integrated inductor circuit comprises multiple through-hole vias that are electrically connected in series to provide an inductance when an electric current is provided to the first integrated inductor circuit.

6. The system of claim 1 , wherein the first integrated inductor circuit includes first and second inductor terminals coupled respectively to the first and second power rails.

7. The system of claim 6 , wherein the first integrated capacitor circuit includes first and second capacitor terminals coupled respectively to the first inductor terminal and a reference ground node.

8. The system of claim 1 , wherein the first and second power rails are coupled to respective first and second consumer circuits, and wherein the first and second consumer circuits operate at different switching frequencies.

9. The system of claim 1 , wherein the first integrated inductor circuit comprises:
a first trace in a first layer and a second trace in a second layer, the second layer spaced apart from and substantially parallel to the first layer; and
a via that electrically couples the first and second traces;
wherein the first and second traces are substantially overlapping and each of the first and second traces comprises multiple turns.

10. The system of claim 1 , wherein the first integrated inductor circuit provides an inductance of about 4 nH.

11. The system of claim 1 , wherein the first integrated inductor circuit has a substantially centrally-located void volume, and wherein the first integrated inductor circuit occupies a landing area of about 1 mm square, and wherein a cross-sectional area of the void volume occupies less than about 20% of the 1 mm square landing area.

12. The system of claim 1 , wherein the first integrated capacitor circuit includes a land-side capacitor circuit disposed on an interconnect side of the semiconductor die.

13. A system comprising:
a processor circuit;
a power converter circuit coupled to the processor circuit and configured to provide, to the processor circuit, regulated DC power supply signals including first and second voltage signals;
wherein the processor circuit comprises a semiconductor die, the semiconductor die including first and second power domains configured to receive the first and second voltage signals, respectively;
wherein each of the first and second power domains includes multiple power rails, configured to provide different power signals to consumer circuits corresponding to the multiple power rails, and wherein each of the multiple power rails is coupled to an adjacent power rail in the same domain or to the power converter circuit using an integrated inductor circuit and an integrated capacitor circuit.

14. The system of claim 13 , wherein the integrated inductor circuit comprises multiple stacked planar traces that are electrically coupled and that are arranged to provide an inductance; and
wherein each of the traces comprises at least one turn of about 90 degrees.

15. The system of claim 13 , wherein the integrated inductor circuit comprises multiple plated through-hole vias that are electrically connected in series to provide an inductance when an electric current is provided to the integrated inductor circuit.

16. A processor circuit comprising:
first and second power domains configured to receive respective power signals from a power converter circuit, wherein the first power domain includes at least first and second power rails configured to provide power signals to respective consumer circuits;
a first integrated inductor circuit coupled between the first and second power rails in the first power domain; and
a first integrated capacitor circuit coupled between the first power rail and a reference ground node.

17. The processor circuit of claim 16 , wherein the first integrated inductor circuit comprises respective traces on multiple stacked circuit layers that are electrically coupled in series to provide an inductance, wherein the multiple stacked traces form a substantially spiral-shaped electrical signal path.

18. The processor circuit of claim 16 , wherein the respective consumer circuits operate at different switching frequencies.

19. The processor circuit of claim 16 , wherein the first integrated inductor circuit comprises:
a first trace in a first layer and a second trace in a second layer, the second layer spaced apart from and substantially parallel to the first layer; and
a via that electrically couples the first and second traces;
wherein the first and second traces are substantially overlapping and each of the first and second traces comprises multiple turns.

20. The processor circuit of claim 16 , wherein the first integrated capacitor circuit includes a land-side capacitor disposed on an interconnect side of a semiconductor die that comprises the processor circuit.

Assignees

• Intel Corp

Inventors

• Tan Fern Nee
• Soman Sanjiv
• Levin Alexander
• Rajagopalan Srinivasan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W44/255

  for operation at multiple different frequencies · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H03K19/00346 Primary

  Modifications for eliminating interference or parasitic voltages or currents · CPC title