Semiconductor package structure

Patent metadata

Field	Value
Publication number	US-10559728-B2
Application number	US-201816113116-A
Country	US
Kind code	B2
Filing date	Aug 27, 2018
Priority date	Aug 27, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A semiconductor package structure is disclosed. The package structure includes a first substrate, a second substrate on which the first substrate is disposed, and a semiconductor chip which is disposed on the first substrate. The two substrates can include two notches or two solder receiving portions. Therefore, when the package structure is disposed on the printed circuit board (PCB), the package structure will protrude less on the surface of the printed circuit board (PCB); or, the solders on the printed circuit board (PCB) will not be shifted by the package structure.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a first substrate, comprising a base portion, a first protrusion and a second protrusion, the base portion comprising a first front surface, a first side surface and a second side surface, the first protrusion and the second protrusion respectively extending from the first side surface and the second side surface, the first protrusion and the second protrusion respectively comprising a first connection surface and a second connection surface, and the first connection surface and the second connection surface respectively connecting to the first side surface and the second side surface;
a second substrate, comprising a second front surface, the first substrate being disposed on a portion of the second front surface, wherein the second substrate further comprises a rear surface and a conductive pattern layer, the rear surface is opposite to the second front surface, and the conductive pattern layer is disposed on the rear surface and the second front surface; and
a semiconductor chip, being disposed on the first front surface of the base portion.

2. The semiconductor package structure of claim 1 , wherein the first substrate further comprises another conductive pattern layer, the another conductive pattern layer is disposed on the first front surface, the first side surface and the second side surface of the base portion, wherein the another conductive pattern layer is electrically connected with the semiconductor chip.

3. The semiconductor package structure of claim 1 , wherein the first substrate further comprises another conductive pattern layer, the another conductive pattern layer is disposed on the first front surface of the base portion the first connection surface of the first protrusion and the second connection surface of the first protrusion and the second protrusion, wherein the another conductive pattern layer is electrically connected with the semiconductor chip.

4. The semiconductor package structure of claim 1 , wherein a first notch and a second notch are defined between the first substrate and the second substrate, the first notch is defined between the second front surface, the first side surface and the first connection surface, and the second notch is defined between the second front surface, the second side surface and the second connection surface.

5. An electronic device, comprising:
a semiconductor package structure which includes:
a first substrate, comprising a base portion, a first protrusion and a second protrusion, the base portion comprising a first front surface, a first side surface and a second side surface, the first protrusion and the second protrusion respectively extending from the first side surface and the second side surface, the first protrusion and the second protrusion respectively comprising a first connection surface and a second connection surface, and the first connection surface and the second connection surface respectively connecting to the first side surface and the second side surface;
a second substrate, comprising a second front surface, the first substrate being disposed on a portion of the second front surface; and
a semiconductor chip, being disposed on the first front surface of the base portion; and

a printed circuit board (PCB), comprising an PCB cutout, the first substrate and the second substrate of the semiconductor package structure being partially located within the PCB cutout, and the semiconductor package structure being electrically connected with the printed circuit board.

6. The electronic device of claim 5 , wherein the printed circuit board further comprises a first supporting portion and a second supporting portion, the first supporting portion and the second supporting portion are separated by the PCB cutout; the first protrusion and the second protrusion are respectively located on the first supporting portion and the second supporting portion.

7. The electronic device of claim 5 , wherein the semiconductor chip is also located within the PCB cutout.

8. The electronic device of claim 5 , wherein the first substrate further comprises a conductive pattern layer, the conductive pattern layer is disposed on the first front surface, the first side surface and the second side surface of the base portion, wherein the conductive pattern layer is electrically connected with the semiconductor chip.

9. The electronic device of claim 8 , wherein the second substrate further comprises a rear surface and another conductive pattern layer, the rear surface is opposite to the second front surface, and the another conductive pattern layer is disposed on the rear surface and the second front surface.

10. The electronic device of claim 9 , wherein a first notch and a second notch are defined between the first substrate and the second substrate, the first notch is defined between the second front surface, the first side surface and the first connection surface, and the second notch is defined between the second front surface, the second side surface and the second connection surface.

11. The electronic device of claim 5 , wherein the first substrate further comprises a conductive pattern layer, the conductive pattern layer is disposed on the first front surface of the base portion, the first connection surface of the first protrusion and the second connection surface of the second protrusion, wherein the conductive pattern layer is electrically connected with the semiconductor chip.

12. The electronic device of claim 11 , wherein the second substrate further comprises a rear surface and another conductive pattern layer, the rear surface is opposite to the second front surface, and the another conductive pattern layer is disposed on the rear surface and the second front surface.

13. The electronic device of claim 12 , wherein a first notch and a second notch are defined between the first substrate and the second substrate, the first notch is defined between the second front surface, the first side surface and the first connection surface, and the second notch is defined between the second front surface, the second side surface and the second connection surface.

14. The electronic device of claim 5 , wherein a first notch and a second notch are defined between the first substrate and the second substrate, the first notch is defined between the second front surface, the first side surface and the first connection surface, and the second notch is defined between the second front surface, the second side surface and the second connection surface.

15. The electronic device of claim 5 , wherein the second substrate further comprises a rear surface and a conductive pattern layer, the rear surface is opposite to the second front surface, and the conductive pattern layer is disposed on the rear surface and the second front surface.

16. The electronic device of claim 6 , wherein a first notch and a second notch are defined between the first substrate and the second substrate, the first notch is defined between the second front surface, the first side surface and the first connection surface, and the second notch is defined between the second front surface, the second side surface and the second connection surface.

17. The electronic device of claim 6 , wherein the second substrate further comprises a rear surface and a conductive pattern layer, the rear surface is opposite to the second front surface, and the conductive pattern layer is disposed on the rear surface and the second front surface.

18. The semiconductor package structure of claim 2 , wherein a

Assignees

• Everlight Electronics Co Ltd

Inventors

• Ho Chih-Ming
• Liang Chun-Chih
• Cherng Ding-Hwa
• Lu Kuang-Mao
• Lo Wen-Chueh
• Yang Hao-Yu
• Kang Chieh-Yu
• Pan Han-Chang

Classifications

• H05K3/34

  by soldering · CPC title

• H05K1/184 Primary

  associated with components inserted in holes through the PCBs and wherein terminals of the components are connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title