Vertical transistor having dual work function materials and method for fabricating thereof

Patent metadata

Field	Value
Publication number	US-10559684-B2
Application number	US-201815916729-A
Country	US
Kind code	B2
Filing date	Mar 9, 2018
Priority date	Apr 7, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A semiconductor device includes a substrate, a semiconductor column vertically disposed on the substrate, a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column, a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column, a gate dielectric material layer on the first insulating material layer and on a portion of sidewalls of the semiconductor column while exposing an upper portion of the semiconductor column, and a gate stack structure on the gate dielectric material layer and surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column. The gate stack structure includes from inside to outside a P-type work function layer, an N-type work function layer, and a gate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a semiconductor column vertically disposed on the substrate;
a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column;
a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column;
a gate dielectric material layer on the first insulating material layer and on a portion of sidewalls of the semiconductor column while exposing an upper portion of the semiconductor column;
a gate stack structure on the gate dielectric material layer and surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column, the gate stack structure comprising, sequentially from inside to outside, a P-type work function layer, an N-type work function layer, and a gate;
the substrate comprises a first PMOS device region having a first PMOS device, a second PMOS device region having a second PMOS device, a first NMOS device region having a first NMOS device, and a second NMOS device region having a second NMOS device;
the semiconductor column comprises a first semiconductor pillar on the first PMOS device region, a second semiconductor pillar on the second PMOS device region, a third semiconductor pillar on the first NMOS device region, and a fourth semiconductor pillar on the second PMOS device region;
the P-type work function layer of the gate stack structure comprises a first P-type work function layer surrounding the first semiconductor pillar, a second P-type work function layer surrounding the second semiconductor pillar, a third P-type work function layer surrounding the third semiconductor pillar, and a fourth P-type work function layer surrounding the fourth semiconductor pillar;
the first PMOS device has a threshold voltage greater than a threshold voltage of the second PMOS device;
the first NMOS device has a threshold voltage greater than a threshold voltage of the second NMOS device; and
the first, second, third, and fourth P-type work function layers are different from each other.

2. The semiconductor device of claim 1 , wherein:
the first P-type work function layer comprises, sequentially from inside to outside, a second TiN layer, a third TiN layer, and a fourth TiN layer;
the second P-type work function layer comprises, sequentially from inside to outside, a first TiN layer, the second TiN layer, the third TiN layer, and the fourth TiN layer;
the third P-type work function layer comprises, sequentially from inside to outside, the third TiN layer, and the fourth TiN layer; and
the fourth P-type work function layer comprises the third TiN layer.

3. The semiconductor device of claim 1 , wherein:
the first P-type work function layer comprises, sequentially from inside to outside, a first TiN layer, a TaN layer, a third TiN layer, and a fourth TiN layer;
the second P-type work function layer comprises, sequentially from inside to outside, the first TiN layer, the TaN layer, a second TiN layer, the third TiN layer, and the fourth TiN layer;
the third P-type work function layer comprises, sequentially from inside to outside, the first TiN layer, the TaN layer, and the fourth TiN layer; and
the fourth P-type work function layer comprises the first TiN layer and the TaN layer.

4. The semiconductor device of claim 1 , wherein:
the first P-type work function layer comprises, sequentially from inside to outside, a first TiN layer, a TaN layer, a third TiN layer, a fourth TiN layer, and a fifth TiN layer;
the second P-type work function layer comprises, sequentially from inside to outside, the first TiN layer, the TaN layer, the third TiN layer, and the fourth TiN layer;
the third P-type work function layer comprises, sequentially from inside to outside, the fourth TiN layer and the fifth TiN layer; and
the fourth P-type work function layer comprises the fifth TiN layer.

5. The semiconductor device of claim 1 , wherein:
the first P-type work function layer comprises, sequentially from inside to outside, a first TiN layer, a TaN layer, and a third TiN layer;
the second P-type work function layer comprises, sequentially from inside to outside, the first TiN layer, the TaN layer, a second TiN layer, and the third TiN layer;
the third P-type work function layer includes, sequentially from inside to outside, the first TiN layer and the TaN layer; and
the fourth P-type work function layer comprises the third TiN layer.

6. The semiconductor device of claim 1 , wherein:
the first P-type work function layer comprises, sequentially from inside to outside, a first TiN layer, a TaN layer, and a third TiN layer;
the second P-type work function layer comprises, sequentially from inside to outside, the first TiN layer, the TaN layer, a second TiN layer, and the third TiN layer;
the third P-type work function layer comprises, sequentially from inside to outside, the first TiN layer and the TaN layer; and
the fourth P-type work function layer comprises the TaN layer.

7. The semiconductor device of claim 1 , further comprising:
a second insulating layer on the gate stack structure having an upper surface flush with an upper surface of the gate dielectric material layer; and
a second contact material layer in contact with the upper portion of the semiconductor column.

8. The semiconductor device of claim 7 , further comprising:
a first contact extending to the first contact material layer;
a second contact extending to the gate; and
a third contact in contact with the second contact material layer.

9. The semiconductor device of claim 1 , wherein the semiconductor column is a nanowire.

10. A method for manufacturing a semiconductor device, comprising:
providing a substrate structure including a substrate, a semiconductor column vertically disposed on the substrate, a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column, a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column, and a gate dielectric material layer on the first insulating material layer and on sidewalls and an upper surface of the semiconductor column; and
forming a gate stack structure on the gate dielectric material layer surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column, the gate stack structure comprising, sequentially from inside to outside, a P-type work function layer, an N-type work function layer, and a gate, wherein:
the substrate comprises a first PMOS device region having a first PMOS device, a second PMOS device region having a second PMOS device, a first NMOS device region having a first NMOS device, and a second NMOS device region having a second NMOS device;
the semiconductor column comprises a first semiconductor pillar on the first PMOS device region, a second semiconductor pillar on the second PMOS device region, a third semiconductor pillar on the first NMOS device region, and a fourth semiconductor pillar on the second PMOS device region;
the P-type work function layer of the gate stack structure comprises a first P-type work function layer surrounding the first semiconductor pillar, a second P-type work function layer surrounding the second semiconductor pillar, a third P-type work function layer surrounding the third semiconductor pillar, and a fourth P-type work function layer surrounding the fourth semiconductor pillar;
the first PMOS device has a threshold voltage greater than a threshold voltage of the second PMOS device;
the first NMOS device has a

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Shen Zhaoxu
• Bei Duohui

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L21/823462

  Electricity · mapped topic

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic