Fabrication of semiconductor junctions

Patent metadata

Field	Value
Publication number	US-10559657-B2
Application number	US-201815970409-A
Country	US
Kind code	B2
Filing date	May 3, 2018
Priority date	Oct 8, 2015
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.

First claim

What is claimed is:

1. A method for fabricating a semiconductor junction, the method comprising:
selectively growing a first semiconductor structure in an elongate tunnel formed of dielectric material extending laterally over a substrate, said first semiconductor structure grown from a seed extending within the elongate tunnel;
removing the seed to expose the first semiconductor structure and create a cavity in the elongate tunnel; and
selectively growing a second semiconductor structure in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.

2. The method as claimed in claim 1 including:
providing a seed material, shaped to define the interior of the elongate tunnel on a first dielectric material layer on the substrate;
depositing a second dielectric material layer in contact with the seed material and first dielectric layer whereby the elongate tunnel comprises the first and second dielectric layers around the seed material;
forming an opening in a first end of the elongate tunnel to expose the seed material; and
etching away a first portion of the seed material via said opening, whereby a remaining portion of the seed material provides said seed.

3. The method as claimed in claim 2 including:
prior to depositing said second dielectric layer, doping a portion of the seed material to produce a doped portion which is resistant to a predetermined etchant; and
etching away said first portion of the seed material using said predetermined etchant whereby said doped portion provides said remaining portion of the seed material.

4. The method as claimed in claim 3 wherein said seed material comprises silicon, said doped portion is produced by boron-doping, and said predetermined etchant comprises tetramethylammonium hydroxide.

5. The method as claimed in claim 3 including:
prior to depositing said second dielectric layer, providing a dummy gate in contact with the seed material such that the dummy gate covers a section of the seed material remote from the ends thereof; and
doping said portion of the seed material such that said doped portion extends between the dummy gate and one end of the seed material;
wherein said opening in said first end of the elongate tunnel exposes the other end of the seed material.

6. The method as claimed in claim 5 including, after growing said second structure, removing the dummy gate and forming a gate structure at the location of the dummy gate.

7. The method as claimed in claim 5 wherein said seed material is shaped into sections along the extent thereof, the sections being of differing width.

8. The method as claimed in claim 7 wherein said seed material is shaped such that said doped portion has a greater width than at least an adjoining section of the seed material.

9. The method as claimed in claim 8 wherein said first portion of the seed material comprises said adjoining section and a further section of greater width than said adjoining section.

10. The method as claimed in claim 1 wherein each of the first and second semiconductor structures comprises a compound semiconductor material.

11. The method as claimed in claim 10 wherein the first and second semiconductor structures comprise the same compound semiconductor material with different doping.

Assignees

• IBM

Inventors

• Borg Mattias
• Moselund Kirsten
• Schmid Heinz
• Riel Heike

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3422

  Antimonides · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title