Panel testing device

Patent metadata

Field	Value
Publication number	US-10559239-B2
Application number	US-201715758869-A
Country	US
Kind code	B2
Filing date	Oct 24, 2017
Priority date	Mar 22, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

Disclosed is a panel testing device. The panel testing device includes: a supporter and a plurality of test pins disposed on the supporter, wherein the plurality of test pins are in one-to-one correspondence with a plurality of signal pins on the tested panel, any one of the test pins satisfies d≤D≤d+L; wherein D is a width of the test pin, d is a width of the signal pin corresponding to the test pin, L is a minimum pitch between two adjacent signal pins.

First claim

The invention claimed is:

1. A panel testing device, comprising:
a supporter; and
a plurality of test pins disposed on the supporter, the plurality of test pins being in one-to-one correspondence with a plurality of signal pins on a tested panel, and any one of the plurality of test pins configured to satisfy:
d≤D≤d+L,

wherein D is a width of the test pin, d is a width of the signal pin in one-to-one correspondence with the test pin, and L is a minimum pitch between two adjacent signal pins.

2. The panel testing device according to claim 1 , wherein two adjacent test pins are disposed on different layers.

3. The panel testing device according to claim 1 , wherein the supporter comprises a slit, and at least one of the plurality of test pins is disposed in the slit.

4. The panel testing device according to claim 1 , wherein the plurality of test pins are parallel to each other.

5. The panel testing device according to claim 1 , further comprising:
a conductor configured to contact with the signal pin, wherein the conductor is disposed on at least one of the plurality of test pins and is electrically connected with the at least one of the plurality of test pins, and the at least one of the plurality of test pins is electrically connected with a corresponding signal pin through the conductor.

6. The panel testing device according to claim 5 , wherein the conductor comprises:
a conductive portion; and
insulating portions, disposed on at least two opposite lateral surfaces of the conductive portion in a first direction and configured to insulate two adjacent conductors in the first direction from each other.

7. The panel testing device according to claim 6 , wherein the conductor further comprises:
an elastic portion, wrapped by the conductive portion.

8. The panel testing device according to claim 5 , wherein the conductor comprises a plurality of conductors, the plurality of conductors are uniformly arranged on the at least one of the plurality of test pins, and at least part of the conductors is electrically connected with the at least one of the plurality of test pins.

9. The panel testing device according to claim 5 , wherein the conductor is in a shape of a sphere or a column.

10. The panel testing device according to claim 1 , wherein the plurality of test pins are disposed on a same side of the supporter, and one of ends of each test pin proximal to the supporter is fixed on the supporter.

11. The panel testing device according to claim 1 , wherein the supporter is in a rectangle plate-shaped.

12. The panel testing device according to claim 1 , wherein an orthographical projection of at least one of the plurality of test pins in a second direction overlaps with an orthographical projection of corresponding signal pin in the second direction, and the second direction is perpendicular to a plane of the tested panel.

13. The panel testing device according to claim 12 , wherein the at least one of the plurality of test pins and the corresponding signal pin are electrically connected with each other through at least one conductor in an overlapping region.

14. The panel testing device according to claim 1 , wherein the plurality of signal pins are arranged equally with a first pitch, the plurality of test pins are arranged equally with a second pitch, and the first pitch is greater than the second pitch.

15. The panel testing device according to claim 2 , wherein the supporter comprises a slit, and at least one of the plurality of test pins is disposed in the slit.

16. A panel testing device, comprising:
a supporter,
a plurality of slits formed in the supporter, any two adjacent slits having different depths; and
a plurality of test pins, each of the plurality of test pins being disposed in a corresponding one of the plurality of slits, the plurality of test pins being in one-to-one correspondence with a plurality of signal pins on a tested panel, and any one of the plurality of test pins being configured to satisfy:
d≤D≤d+L,

wherein D is a width of the test pin, d is a width of the signal pin in one-to-one correspondence with the test pin, and L is a minimum pitch between two adjacent signal pins.

17. The panel testing device according to claim 16 , wherein two test pins respectively disposed in the any two adjacent slits are located at different depth in the supporter.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Ai Yu
• Xie Xuewu
• Liu Bowen
• Sun Shi
• Liu Hao
• Han Kun
• Zhang Ameng

Classifications

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G01R1/06716

  Elastic · CPC title

• G01R1/0425 Primary

  Test clips, e.g. for IC's · CPC title

• G09G2320/0693

  Calibration of display systems · CPC title

• G01R31/3172

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title