Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Patent metadata

Field	Value
Publication number	US-10554496-B2
Application number	US-201514925904-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	May 3, 2013
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.

First claim

What is claimed is:

1. A method, comprising:
generating a floorplan for a chip comprising a plurality of hosts and a network on chip (NoC) interconnect configured to communicatively connect the plurality of hosts, the generating of the floorplan comprising determining, by a processor, positions for the plurality of hosts, a first one of the plurality of hosts having a different physical footprint from a second one of the plurality of hosts, wherein the positions for the plurality of hosts are determined based on optimization of one or more efficiency functions; and
generating the NoC interconnect based on the positions for the plurality of hosts;
wherein the generating the NoC interconnect comprises connecting each of the plurality of hosts to an adjacent router based on the determined positions for the plurality of hosts.

2. The method of claim 1 , wherein the one or more efficiency functions comprises at least one of: latency, bandwidth, and number of router hops between each host in the NoC interconnect.

3. The method of claim 1 , further comprising determining whether resulting positions of the plurality of hosts results in overlap and repositioning overlapped ones of the plurality of hosts.

4. The method of claim 3 , wherein the repositioning overlapped ones of the plurality of hosts comprises:
determining whether resulting positions of the plurality of hosts results in overlap, and repositioning overlapped ones of the plurality of hosts by one of: repositioning overlapped ones to the position associated with the selected host, and selecting the overlapped ones for shifting in the selected direction.

5. The method of claim 1 , wherein the determining positions for the plurality of hosts is based on connectivity requirements of the plurality of hosts.

6. A non-transitory computer readable medium, storing instructions for executing a process, the instructions comprising:
generating a floorplan for a chip comprising a plurality of hosts and a network on chip (NoC) interconnect configured to communicatively connect the plurality of hosts, the generating of the floorplan comprising determining positions for the plurality of hosts, a first one of the plurality of hosts having a different physical footprint from a second one of the plurality of hosts, wherein the positions for the plurality of hosts are determined based on optimization of one or more efficiency functions; and
generating the NoC interconnect based on the positions for the plurality of hosts;
wherein the generating the NoC interconnect comprises connecting each of the plurality of hosts to an adjacent router based on the determined positions for the plurality of hosts.

7. The non-transitory computer readable medium of claim 6 , wherein the one or more efficiency functions comprises at least one of: latency, bandwidth, and number of router hops between each host in the NoC interconnect.

8. The non-transitory computer readable medium of claim 6 , wherein the instructions further comprise determining whether resulting positions of the plurality of hosts results in overlap and repositioning overlapped ones of the plurality of hosts.

9. The non-transitory computer readable medium of claim 8 , wherein the repositioning overlapped ones of the plurality of hosts comprises:
determining whether resulting positions of the plurality of hosts results in overlap, and repositioning overlapped ones of the plurality of hosts by one of: repositioning overlapped ones to the position associated with the selected host, and selecting the overlapped ones for shifting in the selected direction.

10. The non-transitory computer readable medium of claim 6 , wherein the determining positions for the plurality of hosts is based on connectivity requirements of the plurality of hosts.

11. A system, comprising:
a memory; and
a processor, configured to:
generate a floorplan for a chip comprising a plurality of hosts and a network on chip (NoC) interconnect configured to communicatively connect the plurality of hosts, the processor configured to generate the floorplan by determining positions for the plurality of hosts, wherein a first one of the plurality of hosts having a different physical footprint from a second one of the plurality of hosts, wherein the positions for the plurality of hosts are determined based on optimization of one or more efficiency functions; and
generate the NoC interconnect based on the positions for the plurality of hosts;
wherein the processor is configured to generate the NoC interconnect by connecting each of the plurality of hosts to an adjacent router based on the determined positions for the plurality of hosts.

12. The system of claim 11 , wherein the one or more efficiency functions comprises at least one of: latency, bandwidth, and number of router hops between each host in the NoC interconnect.

13. The system of claim 11 , wherein the processor is configured to determine whether resulting positions of the plurality of hosts results in overlap and reposition overlapped ones of the plurality of hosts.

14. The system of claim 11 , wherein the processor is configured to reposition overlapped ones of the plurality of hosts by:
determining whether resulting positions of the plurality of hosts results in overlap, and repositioning overlapped ones of the plurality of hosts by one of: repositioning overlapped ones to the position associated with the selected host, and selecting the overlapped ones for shifting in the selected direction.

15. The system of claim 11 , wherein the processor is configured to determine positions for the plurality of hosts based on connectivity requirements of the plurality of hosts.

Assignees

• Netspeed Systems

Inventors

• Norige Eric
• Kumar Sailesh

Classifications

• H04L45/06 Primary

  Deflection routing, e.g. hot-potato routing · CPC title

• H04L41/147

  for predicting network behaviour · CPC title

• H04L41/12 Primary

  Discovery or management of network topologies · CPC title