Solid state switch system

Patent metadata

Field	Value
Publication number	US-10554201-B2
Application number	US-201715495091-A
Country	US
Kind code	B2
Filing date	Apr 24, 2017
Priority date	Jul 22, 2016
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A solid state switch for connecting and disconnecting an electrical device has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. A gate driver is operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device. The gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device.

First claim

What is claimed is:

1. A solid state switch system for connecting and disconnecting an electrical device to/from a power source, comprising:
a first terminal constructed for coupling to and receiving power from a power source;
a second terminal constructed for delivering power from the power source to the electrical device;
at least one FET-type device coupled to the first terminal and the second terminal;
at least one thyristor-type device coupled to the first terminal and the second terminal in parallel to the at least one FET-type device; and
a gate driver operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device; wherein the gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device,
wherein the gate driver is operative to receive a command signal to supply current to the electrical device, and
wherein the gate driver is constructed to either:
(1) delay a control signal to turn on the at least one FET-type device by a first time delay from the start of the command signal and wherein the gate driver is constructed to delay a control signal to turn on the at least one thyristor-type device by a second time delay from the start of the command signal, or
(2) delay a control signal to turn off the at least one FET-type device by a third time delay from the end of the command signal, and wherein the gate driver is constructed to delay a control signal to turn off the at least one thyristor-type device by a fourth time delay from the end of the command signal.

2. The solid state switch system of claim 1 , wherein the split depends upon a magnitude of the current.

3. The solid state switch system of claim 1 , wherein the gate driver is constructed to provide a first set of gate drive signals to the at least one FET-type device and to the at least one thyristor-type device under nominal current conditions; wherein the gate driver is constructed to provide a second set of gate drive signals to the at least one FET-type device and to the at least one thyristor-type device under surge current conditions; and wherein the second set of gate drive signals is different than the first set of gate drive signals.

4. The solid state switch system of claim 3 , the electrical device having a rated current, wherein the nominal current conditions are a current flow at approximately the rated current or less.

5. The solid state switch system of claim 3 , wherein the first set of gate drive signals is operative to direct the current through each of the at least one FET-type device and the at least one thyristor-type device during the nominal current conditions.

6. The solid state switch system of claim 3 , wherein the first set of gate drive signals is operative to direct the current through only the at least one FET-type device during the nominal current conditions.

7. The solid state switch system of claim 3 , wherein the second set of gate drive signals is operative to direct the current through each of the at least one FET-type device and the at least one thyristor-type device during the surge current conditions.

8. The solid state switch system of claim 3 , wherein the second set of gate drive signals is operative to the direct the current through only the at least one thyristor-type device during the surge current conditions.

9. The solid state switch system of claim 1 , wherein the first time delay and the second time delay are configured to direct the at least one FET-type device and the at least one thyristor-type device to turn on simultaneously.

10. The solid state switch system of claim 1 , wherein the second time delay is greater than the first time delay.

11. The solid state switch system of claim 1 , wherein the first time delay is greater than the second time delay.

12. The solid state switch system of claim 1 , wherein the fourth time delay is greater than the third time delay.

13. The solid state switch system of claim 1 , wherein the third time delay is greater than the second time delay.

14. The solid state switch system of claim 1 , wherein the gate driver is constructed to turn on the at least one thyristor-type device simultaneously with turning off the at least one FET-type device in response to the end of the command signal.

15. A solid state switch system for connecting and disconnecting an electrical device to/from a power source, comprising:
a first terminal constructed for coupling to and receiving power from a power source;
a second terminal constructed for delivering power from the power source to the electrical device;
at least one FET-type device coupled to the first terminal and the second terminal;
at least one thyristor-type device coupled to the first terminal and the second terminal in parallel to the at least one FET-type device; and
a gate driver operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device; wherein the gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device,
wherein the gate driver is operative to receive a command to stop supplying the current to the electrical device; and wherein the gate driver is constructed to:
(1) turn off the at least one FET-type device in response to the command while the at least one thyristor-type device is still turned on, or
(2) simultaneously turn off the at least one FET-type device and turn on the at least one thyristor-type device in response to the command.

16. A solid state switch system for connecting and disconnecting an electrical device to/from a power source, comprising:
a first terminal constructed for coupling to and receiving power from a power source;
a second terminal constructed for delivering power from the power source to the electrical device;
at least one FET-type device coupled to the first terminal and the second terminal;
at least one thyristor-type device coupled to the first terminal and the second terminal in parallel to the at least one FET-type device; and
a gate driver operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device; wherein the gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device,
wherein the at least one FET-type device has a first power loss profile based on the rated current associated with the electrical device; wherein the at least one thyristor-type device has a second power loss profile based on an inrush current and a start current associated with the electrical device; and wherein the gate driver is constructed to control a split of the current based on a threshold determined via a correlation between the first power loss profile and the second power loss profile.

17. A solid state switch system for connecting and disconnecting an electrical device to/from a power source, comprising:
a command input operative to provide a command signal for commanding connection or disconnection of the electrical device;
at least one FET-type device coupled to the electrical device and the power source;
at least one thyristor-type device coupled to the electrical device and the power source in parallel to the at least one FET-type device;
a first gate driver circuit coupl

Assignees

• Abb Schweiz Ag

Inventors

• Cairoli Pietro
• Hofstetter Lukas
• Bator Matthias
• Bini Ricardo
• Rahimo Munaf

Classifications

• H03K17/6872

  using complementary field-effect transistors · CPC title

• H03K17/567

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H03K2017/6875

  using self-conductive, depletion FETs · CPC title

• H03K2217/0036

  Means reducing energy consumption · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title