Analog-to-digital converters and methods

Patent metadata

Field	Value
Publication number	US-10554186-B2
Application number	US-201715845218-A
Country	US
Kind code	B2
Filing date	Dec 18, 2017
Priority date	Apr 21, 2014
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A circuit includes a first integration stage, a quantizer, a second integration stage coupled between the first integration stage and the quantizer, and a digital-to-analog converter (DAC). The first integration stage includes a first input node pair configured to receive a pair of differential analog input signals, and the quantizer is configured to generate a digital signal based on the pair of differential analog input signals and a clock signal. The second integration stage includes a second input node pair, and the DAC is configured to receive the digital signal and output feedback signals to at least one input node pair of the first input node pair or the second input node pair.

First claim

What is claimed is:

1. A circuit comprising:
a reference node configured to have a reference ground level;
a first integration stage comprising a first input node pair configured to receive a pair of differential analog input signals and first feedback signals based on a digital signal;
a quantizer configured to generate the digital signal based on the pair of differential analog input signals and a clock signal;
a pair of feedback paths configured to provide the first feedback signals to the first input node pair, each feedback path of the pair of feedback paths being coupled to the reference node by a resistive device;
a second integration stage coupled between the first integration stage and the quantizer, the second integration stage comprising a second input node pair; and
a digital-to-analog converter (DAC) configured to receive the digital signal and output second feedback signals to the first input node pair.

2. The circuit of claim 1 , wherein each integration stage of the first integration stage and the second integration stage further comprises:
an operational amplifier;
a first capacitive device coupled between an inverted input node of the operational amplifier and a first output node of the operational amplifier; and
a second capacitive device coupled between a non-inverted input node of the operational amplifier and a second output node of the operational amplifier.

3. The circuit of claim 1 , wherein the quantizer is a one-bit quantizer.

4. The circuit of claim 1 , wherein the quantizer comprises a comparator.

5. The circuit of claim 1 , wherein
the quantizer is configured to sample a differential input signal at a sampling frequency of the clock signal,
the sampling frequency is not less than a predetermined multiple of an upper bandwidth frequency of the pair of differential analog input signals, and
the predetermined multiple has a value of at least two.

6. The circuit of claim 1 , wherein
the DAC comprises a first output node and a second output node configured to output the second feedback signals, and
the DAC is configured to, based on the digital signal, inject a reference current level to one of the first output node or the second output node, and extract the reference current level from the other of the first output node or the second output node.

7. The circuit of claim 6 , wherein the DAC comprises an input configured to receive a reference voltage level, and the reference current level is determined by the reference voltage level.

8. The circuit of claim 1 , wherein
the circuit comprises another DAC configured to output third feedback signals to the second input node pair.

9. An analog-to-digital converter (ADC) circuit comprising:
a first integration stage comprising a first input node pair configured to receive a pair of differential input signals, and a first output node pair;
a second integration stage comprising a second input node pair coupled to the first output node pair, and a second output node pair;
a quantizer comprising a third input node pair coupled to the second output node pair, the quantizer configured to generate a digital signal based on the pair of differential input signals; and
a digital-to-analog converter (DAC) configured to receive the digital signal and output a first pair of feedback signals to the first input node pair,
wherein the ADC circuit is a portion of an amplifier comprising a pair of output nodes configured to be continuously coupled to the first input node pair, the first input node pair thereby being configured to receive a second pair of feedback signals based on the digital signal.

10. The ADC circuit of claim 9 , wherein
the first integration stage further comprises:
a first operational amplifier coupled between the first input node pair and the first output node pair; and
a first pair of capacitive devices coupled between the first input node pair and the first output node pair, and the second integration stage further comprises:
a second operational amplifier coupled between the second input node pair and the second output node pair; and
a second pair of capacitive devices coupled between the second input node pair and the second output node pair.

11. The ADC circuit of claim 9 , wherein the second input node pair is coupled to the first output node pair through a pair of resistive devices.

12. The ADC circuit of claim 9 , wherein the ADC circuit is a continuous-time ADC having a sampling frequency based on a clock signal received by the quantizer.

13. The ADC circuit of claim 9 , wherein the DAC is configured to
generate a reference current level from a reference voltage level, and
based on the digital signal, inject the reference current level at one input node of the first input node pair, and extract the reference current level from the other input node of the first input node pair.

14. The ADC circuit of claim 9 , wherein
the amplifier is a class-D amplifier, and
the second pair of feedback signals is generated from a pair of output signals of the class-D amplifier.

15. The ADC circuit of claim 9 , wherein the digital signal is expressed in the Z-domain as an error signal summed with a product of a quantization error and a noise transfer function, the error signal being a Z-domain summation comprising the second pair of feedback signals.

16. A method, comprising:
receiving, by an analog-to-digital converter (ADC), a differential input signal based on an analog input signal, a first feedback signal pair, and a second feedback signal pair;
generating, by the ADC, a digital signal based on the differential input signal;
generating, by a digital-to-analog converter (DAC), the first feedback signal pair based on the digital signal; and
using an amplifier to generate the second feedback signal pair based on the digital signal and continuously provide the second feedback signal pair to the ADC,
wherein the generating the digital signal by the ADC comprises performing an anti-aliasing filtering based on the combined differential input signal, first feedback signal pair, and second feedback signal pair.

17. The method of claim 16 , wherein the generating the digital signal is based on operating a quantizer in a continuous-time mode based on a sampling frequency of a clock signal.

18. The method of claim 16 , wherein the generating the first feedback signal pair by the DAC comprises injecting a reference current level at one input node of an input node pair configured to receive the differential input signal, and extracting the reference current level from the other input node of the input node pair configured to receive the differential input signal.

19. The method of claim 16 , wherein the using the amplifier to generate the second feedback signal pair further comprises:
generating a class-D amplifier output signal based on the digital signal; and
generating the second feedback signal pair from the class-D amplifier output signal.

20. The method of claim 16 , wherein the performing the anti-aliasing filtering comprises receiving the combined differential input signal, first feedback signal pair, and second feedback signal pair at inverting and non-inverting input nodes of an operational amplifier, wherein a first capacitive device is coupled between the inverting input node and a first output node of the operational amplifier, and a second capacitive device is coupled between the non-inverting input node and a second output node of the operational amplifier.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kinyua Martin
• Soenen Eric

Classifications

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03M3/434

  with multi-level feedback · CPC title

• H03F2200/135

  there being a feedback over one or more internal stages in the global amplifier · CPC title