Multiple stacked field-plated GaN transistor and interlayer dielectrics to improve breakdown voltage and reduce parasitic capacitances

Patent metadata

Field	Value
Publication number	US-10553689-B2
Application number	US-201515777140-A
Country	US
Kind code	B2
Filing date	Dec 23, 2015
Priority date	Dec 23, 2015
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Embodiments of the invention include a high voltage transistor with one or more field plates and methods of forming such transistors. According to an embodiment, the transistor may include a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region. Embodiments of the invention may also include a first interlayer dielectric (ILD) formed over the channel region and a second ILD formed over the first ILD. According to an embodiment, a first field plate may be formed in the second ILD. In an embodiment the first field plate is not formed as a single bulk conductive feature with the gate electrode. In some embodiments, the first field plate may be electrically coupled to the gate electrode by one or more vias. In alternative embodiments, the first field plate may be electrically isolated from the gate electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region;
a first interlayer dielectric (ILD) formed over the channel region;
a second ILD formed over the first ILD; and
a first field plate formed in the second ILD, wherein the first field plate is not formed as a single bulk conductive feature with the gate electrode, and wherein a top surface of the first field plate is substantially coplanar with a top surface of the second ILD.

2. The semiconductor device of claim 1 , wherein the first field plate is coupled to the gate electrode or the source electrode with one or more vias.

3. The semiconductor device of claim 1 , wherein the first field plate is not electrically coupled to the gate electrode, and not electrically coupled to the source electrode.

4. The semiconductor device of claim 1 , wherein the first ILD is a different material than the second ILD.

5. The semiconductor device of claim 1 , further comprising:
a third ILD; and
a second field plate formed in the third ILD, wherein the second field plate is not formed as a single bulk conductive feature with the gate electrode or the first field plate.

6. The semiconductor device of claim 5 , wherein the first field plate and the second field plate do not substantially overlap each other.

7. The semiconductor device of claim 5 , wherein an outermost edge of the second field plate is closer to a centerline of the gate electrode than an outermost edge of the first field plate.

8. The semiconductor device of claim 5 , wherein the first field plate and the second field plate are electrically coupled together by one or more vias.

9. The semiconductor device of claim 8 , wherein the first field plate and the second field plate are electrically coupled to the gate electrode by one or more vias, or the first field plate and the second field plate are electrically coupled to the source electrode by one or more vias.

10. The semiconductor device of claim 5 , wherein the first field plate and the second field plate are the same material, and wherein the first field plate and the second field plate are a different material than the gate electrode.

11. The semiconductor device of claim 5 , wherein the first field plate and the second field plate are not electrically coupled together.

12. The semiconductor device of claim 11 , wherein one of the first field plate and the second field plate is electrically coupled to the gate electrode, and the other of the first field plate and the second field plate is electrically coupled to the source electrode.

13. A method of forming electric field plates over a transistor, comprising:
forming a transistor that includes a source region, a drain region, a channel region between the source and drain region, and a gate electrode over the channel region;
forming a first interlayer dielectric (ILD) over the channel region;
forming a second ILD over the first ILD;
patterning the second ILD to form a first field plate opening;
depositing a conductive material into the first field plate opening to form a first field plate;
forming a third ILD over the second ILD and the first field plate;
patterning the third ILD to form a second field plate opening; and
depositing a conductive material into the second field plate opening to form a second field plate.

14. The method of claim 13 , wherein the first ILD is formed with a sputtering or chemical vapor deposition process.

15. The method of claim 13 , wherein the first ILD is a different material than the second ILD.

16. The method of claim 13 , wherein the first field plate opening is patterned at the same time one or more interconnect line openings are patterned in the second ILD, and wherein the first field plate is deposited at the same time the interconnect lines are formed in the second ILD.

17. The method of claim 16 , wherein the second field plate opening is patterned at the same time one or more interconnect line openings are patterned in the third ILD, and wherein the second field plate is deposited at the same time the interconnect lines are formed in the third ILD.

18. The method of claim 13 , wherein the gate electrode is a different material than the first field plate and the second field plate.

19. The method of claim 13 , wherein the first field plate and the second field plate are not electrically coupled to the gate electrode, and not electrically coupled to the source electrode.

20. The method of claim 13 , wherein the first field plate and the second field plate are electrically coupled by one or more vias.

21. The method of claim 20 , wherein the first field plate and the second field plate are electrically coupled to the gate electrode or the source electrode by one or more vias.

22. The method of claim 13 , wherein one of the first field plate and the second field plate is electrically coupled to the gate electrode, and the other of the first field plate and the second field plate is electrically coupled to the source electrode.

23. The method of claim 13 , wherein the channel region is GaN.

24. A semiconductor device comprising:
a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region, wherein the channel region is GaN, and wherein a polarization layer is formed over a top surface of the channel region;
a first interlayer dielectric (ILD) formed over the channel region;
a second ILD formed over the first ILD, wherein the first ILD has a lower k-value than the second ILD;
a first field plate formed in the second ILD, wherein the first field plate is not formed as a single bulk conductive feature with the gate electrode;
a third ILD; and
a second field plate formed in the third ILD, wherein the second field plate is not formed as a single bulk conductive feature with the gate electrode or the first field plate.

25. The semiconductor device of claim 21 , wherein the first field plate and the second field plate are electrically coupled together by one or more vias.

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Gardner Sanaz K
• Sung Seung Hoon

Classifications

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H01L21/765

  Electricity · mapped topic

• H01L29/66462

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic