Semiconductor device having multiple semiconductor chips laminated together and electrically connected

Patent metadata

Field	Value
Publication number	US-10553560-B2
Application number	US-201414776863-A
Country	US
Kind code	B2
Filing date	Mar 18, 2014
Priority date	Mar 18, 2013
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor chip having a substrate, a circuit-forming layer formed on one surface of the substrate, first bump electrodes formed on an electrode pad arranged on the circuit-forming layer, second bump electrodes formed on the other surface of the substrate, and first through-electrodes electrically connecting the first bump electrodes to the second bump electrodes; and
a second semiconductor chip having a substrate comprising a first surface and a second surface, the second surface being opposite to the first surface, a circuit-forming layer formed on the first surface of the substrate, third bump electrodes formed on an electrode pad arranged on the circuit-forming layer, fourth bump electrodes formed on the second surface of the substrate, and second through-electrodes electrically connecting the third bump electrodes to the fourth bump electrodes, wherein a number of the fourth bump electrodes is fewer than a number of the third bump electrodes, and a number of the second through-electrodes is fewer than a number of the first through-electrodes; and including:
a chip laminate having the first semiconductor chip and the second semiconductor chip laminated together so that the one surface of the first semiconductor chip faces the first surface of the second semiconductor chip;
the first semiconductor chip having a plurality of first reinforcing bump electrodes formed on the one surface of the substrate, a plurality of second reinforcing bump electrodes formed on the other surface of the substrate, the plurality of second reinforcing bump electrodes being arranged in locations overlapping the respective first reinforcing bump electrodes;
wherein the first and second reinforcing bump electrodes are disposed outside the periphery of the second semiconductor chip as seen in plan view.

2. The semiconductor device as claimed in claim 1 , comprising a wiring substrate having a connection pad formed on one surface, and the chip laminate is mounted on the one surface of the wiring substrate so that the one surface of the wiring substrate faces the second surface of the second semiconductor chip, and the connection pad is electrically connected to the fourth bump electrodes.

3. The semiconductor device as claimed in claim 1 , wherein the first reinforcing bump electrodes are arranged in a row direction along one side of the first semiconductor chip; and a first spacing between the fourth bump electrodes in the row direction is wider than a second spacing between the third bump electrodes in the row direction.

4. The semiconductor device as claimed in claim 1 , wherein:
the first through-electrodes and the second bump electrodes of the first semiconductor chip are arranged in locations overlapping the first bump electrodes as seen in plan view; and
the second through-electrodes and the fourth bump electrodes of the second semiconductor chip are arranged in locations not overlapping the third bump electrodes as seen in plan view.

5. The semiconductor device of claim 3 , wherein no third bump electrode is disposed between the fourth bump electrodes and a respective side of the second semiconductor chip as seen in plan view.

6. The semiconductor device of claim 3 , wherein the fourth bump electrodes are disposed along opposite sides of the second semiconductor chip, and wherein no third bump electrode is disposed between the fourth bump electrodes and a respective side of the second semiconductor chip as seen in plan view.

7. The semiconductor device of claim 1 , further comprising a plurality of reinforcing through-electrodes in the first semiconductor chip, the plurality of reinforcing through-electrodes respectively connecting first reinforcing bump electrodes with second reinforcing bump electrodes.

8. The semiconductor device of claim 1 , wherein the first reinforcing bump electrodes are arranged in a row direction along opposite sides of the first semiconductor chip.

9. A semiconductor device comprising:
a first semiconductor chip having a substrate, a circuit-forming layer formed on one surface of the substrate, first bump electrodes formed on an electrode pad arranged on the circuit-forming layer, second bump electrodes formed on the other surface of the substrate, and first through-electrodes electrically connecting the first bump electrodes to the second bump electrodes;
a second semiconductor chip having a substrate comprising a first surface and a second surface, the second surface being opposite the first surface, a circuit-forming layer formed on the first surface of the substrate, third bump electrodes formed on an electrode pad arranged on the circuit-forming layer, fourth bump electrodes formed on the second surface of the substrate, and second through-electrodes electrically connecting the third bump electrodes to the fourth bump electrodes, wherein a number of the fourth bump electrodes is fewer than a number of the third bump electrodes, and a number of the second through-electrodes is fewer than a number of the first through-electrodes;
a third semiconductor chip having a substrate, a circuit-forming layer formed on one surface of the substrate, and fifth bump electrodes formed on an electrode pad arranged on the circuit-forming layer;
a wiring substrate comprising an insulating base material and having a connection pad formed on one surface; and
a chip laminate formed by laminating together the first semiconductor chip and the second semiconductor chip so that the one surface of the first semiconductor chip faces the first surface of the second semiconductor chip, and the first bump electrodes are electrically connected to the third bump electrodes such that the first bump electrodes contact the third bump electrodes via a conductive solder layer, and the third semiconductor chip is laminated to the first semiconductor chip so that the other surface of the first semiconductor chip faces the circuit-forming layer of the third semiconductor chip, and the second bump electrodes are electrically connected to the fifth bump electrodes;
wherein the chip laminate is mounted on the one surface of the wiring substrate so that the one surface of the wiring substrate faces the second surface of the second semiconductor chip;
the first semiconductor chip having a plurality of first reinforcing bump electrodes formed on the one surface of the substrate, a plurality of second reinforcing bump electrodes formed on the other surface of the substrate, the plurality of second reinforcing bump electrodes being arranged in locations overlapping the respective first reinforcing bump electrodes;
wherein the first and second reinforcing bump electrodes are disposed outside the periphery of the second semiconductor chip as seen in plan view.

10. The semiconductor device as claimed in claim 9 , wherein the thickness of the third semiconductor chip is thicker than the thickness of the first semiconductor chip seen in the lamination direction of the first semiconductor chip and the third semiconductor chip.

11. The semiconductor device as claimed in claim 9 , wherein:
the first through-electrodes and the second bump electrodes of the first semiconductor chip are arranged in locations overlapping the first bump electrodes as seen in plan view; and
the second through-electrodes and the fourth bump electrodes of the second semiconductor chip are arranged in locations not overlapping the third bump electrodes as seen in plan view.

12. The semiconductor device as claimed in claim 9 , wherein the first reinforcing bump electrodes are arranged in a row direction along one side of the first semiconductor chip; and a first spacing

Assignees

• Ps4 Luxco Sarl
• Longitude Licensing Ltd

Inventors

• Watanabe Mitsuhisa

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title