Multilayer ceramic capacitor, multilayer ceramic capacitor series including the same, and multilayer ceramic capacitor mount body including the same

Patent metadata

Field	Value
Publication number	US-10553360-B2
Application number	US-201715666594-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Aug 13, 2014
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a body that includes a plurality of dielectric layers and a plurality of conductive layers stacked on each other in a stacking direction and that includes first and second main surfaces opposing each other in the stacking direction, first and second end surfaces opposing each other in a length direction and connecting the first and second main surfaces, and first and second side surfaces opposing each other in a width direction and connecting the first and second main surfaces and the first and second end surfaces; and
first and second outer electrodes that are disposed on portions of a surface of the body and oppose each other in the length direction; wherein
the body includes a first outer layer portion including a first of the plurality of dielectric layers defining the first main surface, a second outer layer portion including a second of the plurality of dielectric layers defining the second main surface, and an inner layer portion adjacent to both of the first outer layer portion and the second outer layer portion, the inner layer portion includes a portion extending from a first outermost conductive layer positioned closest to the first main surface among the plurality of conductive layers through a second outermost conductive layer positioned closest to the second main surface among the plurality of conductive layers in the stacking direction;
a dimension of the body in the width direction is at least 20% greater than a dimension of the body in the stacking direction;
the dimension of the body in the width direction is smaller than a dimension of the body in the length direction;
the second outer layer portion includes an outer portion including the second main surface and an inner portion adjacent to both of the outer portion and the inner layer portion;
each of the inner portion and the outer portion includes Si as a secondary component;
a molar ratio of the Si included in the outer portion is higher than a molar ratio of the Si included in the inner portion;
a dimension of the second outer layer portion in the stacking direction is greater than a dimension of the first outer layer portion in the stacking direction;
a total dimension of the first outer layer portion and the second outer layer portion in the stacking direction is smaller than a dimension of the inner layer portion in the stacking direction;
a color of the second main surface is different from a color of the first main surface; and
a composition of a dielectric material of the plurality of dielectric layers included in the inner layer portion is the same as a composition of a dielectric material of the first plurality of dielectric layers included in the first outer layer portion.

2. The multilayer ceramic capacitor according to claim 1 , wherein the dimension of the inner layer portion in the stacking direction is smaller than a dimension of a portion of the inner layer portion where the plurality of conductive layers are stacked in the width direction.

3. The multilayer ceramic capacitor according to claim 1 , wherein the body includes side gaps between each of the first and second side surfaces and the inner layer portion, and a maximum dimension or an average dimension of the side gaps in the width direction is greater than about 30 μm and less than about 90 μm.

4. The multilayer ceramic capacitor according to claim 1 , wherein the outer portion includes a boundary region adjacent to the inner portion, and, when viewed from the width direction, the boundary region includes a portion that inclines toward the first main surface as the boundary region gets closer to one of the first and second end surfaces.

5. The multilayer ceramic capacitor according to claim 1 , wherein the dimension of the body in the width direction is greater than about 0.9 mm and the dimension of the body in the stacking direction is smaller than about 0.9 mm.

6. The multilayer ceramic capacitor according to claim 1 , wherein the dimension of the second outer layer portion in the stacking direction is about 90 μm or greater and is equal to or smaller than about ¼ of the dimension of the inner layer portion in the stacking direction.

7. The multilayer ceramic capacitor according to claim 1 , wherein the body includes side gaps between each of the first and second side surfaces and the inner layer portion, and an average dimension of the side gaps in the width direction is greater than the dimension of the first outer layer portion in the stacking direction.

8. The multilayer ceramic capacitor according to claim 1 , wherein the dimension of the first outer layer portion in the stacking direction is about 10 μm or greater, and the dimension of the second outer layer portion in the stacking direction is about 90 μm or greater.

9. A multilayer ceramic capacitor mount body comprising:
the multilayer ceramic capacitor according to claim 1 ; and
a substrate on which the multilayer ceramic capacitor is mounted; wherein
the second main surface of the multilayer ceramic capacitor faces the substrate.

10. The multilayer ceramic capacitor mount body according to claim 9 , wherein
the substrate includes two lands on a surface of the substrate, the two lands being electrically connected to the first and second outer electrodes of the multilayer ceramic capacitor, respectively; and
a dimension of each of the two lands in the width direction of the body is smaller than the dimension of the body in the width direction.

11. The multilayer ceramic capacitor mount body according to claim 10 , wherein, the width of each of the two lands in the width direction is smaller than the dimension of the inner layer portion in the width direction.

12. A multilayer ceramic capacitor comprising:
a body that includes a plurality of dielectric layers and a plurality of conductive layers stacked on each other in a stacking direction and that includes first and second main surfaces opposing each other in the stacking direction, first and second end surfaces opposing each other in a length direction and connecting the first and second main surfaces, and first and second side surfaces opposing each other in a width direction and connecting the first and second main surfaces and the first and second end surfaces; and
first and second outer electrodes that are disposed on portions of a surface of the body and oppose each other in the length direction; wherein
the body includes a first outer layer portion including a first of the plurality of dielectric layers defining the first main surface, a second outer layer portion including a second of the plurality of dielectric layers defining the second main surface, and an inner layer portion adjacent to both of the first outer layer portion and the second outer layer portion, the inner layer portion includes a portion extending from a first outermost conductive layer positioned closest to the first main surface among the plurality of conductive layers through a second outermost conductive layer positioned closest to the second main surface among the plurality of conductive layers in the stacking direction;
a dimension of the body in the width direction is at least 20% greater than a dimension of the body in the stacking direction;
the dimension of the body in the width direction is smaller than a dimension of the body in the length direction;
the second outer layer portion includes an outer portion including the second main surface and an inner portion adjacent to both of the outer portion and the inner layer portion;
each of the inner portion and the outer portion includes Si as a secondary component;
a molar ratio of the Si included in th

Assignees

• Murata Manufacturing Co

Inventors

• Kitano Shota
• Katsuyama Takanobu
• Sugita Hiroaki

Classifications

• H01G4/38

  Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/1209

  characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title