Tailoring timing offsets during a programming pulse for a memory device

Patent metadata

Field	Value
Publication number	US-10553286-B2
Application number	US-201816147422-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells; and
a memory controller comprising logic to:
receive a request to program a memory cell within the array of memory cells;
select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells; and
initiate, in response to the request, the programming pulse with the one or more selected timing offsets to program the memory cell within the array of memory cells.

2. The memory device of claim 1 , wherein the memory controller further comprises logic to select the one or more timing offsets between multiple signals of the programming pulse, wherein the multiple signals of the programming pulse include a first signal that corresponds to a path resistance for the memory cell transitioning from high to low, a second signal that corresponds to a voltage bias that is supplied to the memory cell transitioning from low to high, and a third signal that corresponds to a current mirror transitioning from off to on.

3. The memory device of claim 2 , wherein the one or more timing offsets includes a first timing offset between the first signal that corresponds to the path resistance and the second signal that corresponds to the voltage bias, and a second timing offset between the second signal that corresponds to the voltage bias and the third signal that corresponds to the current mirror.

4. The memory device of claim 3 , wherein the second timing offset is equal to zero when the second signal and the third signal occur at a same time.

5. The memory device of claim 2 , wherein the one or more timing offsets includes a first timing offset between the second signal that corresponds to the voltage bias and the first signal that corresponds to the path resistance, and a second timing offset between the first signal that corresponds to the path resistance and the third signal that corresponds to the current mirror.

6. The memory device of claim 5 , wherein the second timing offset is equal to zero when the first signal and the third signal occur at a same time.

7. The memory device of claim 2 , wherein the one or more timing offsets are equal to zero when the first signal, the second signal and the third signal occur at a same time.

8. The memory device of claim 1 , wherein the memory controller further comprises logic to:
determine the polarity of access for the memory cell to be positive when a memory address of the memory cell is associated with a positive polarity deck;
determine the polarity of access for the memory cell to be negative when the memory address of the memory cell is associated with a negative polarity deck; and
select the one or more timing offsets for the programming pulse in accordance with the polarity of access being positive or the polarity of access being negative.

9. The memory device of claim 8 , wherein the memory controller further comprises logic to select decreased timing offsets for the programming pulse when the polarity of access for the memory cell is negative and increased timing offsets when the polarity of access for the memory cell is positive.

10. The memory device of claim 1 , wherein the memory controller further comprises logic to:
determine the number of prior write cycles for the memory cell; and
select increased timing offsets or decreased timing offsets for the programming pulse depending on the number of prior write cycles for the memory cell.

11. The memory device of claim 1 , wherein the memory controller further comprises logic to:
determine the number of prior write cycles for the memory cell;
select decreased timing offsets for the programming pulse when the number of prior write cycles for the memory cell is increased; and
select increased timing offsets for the programming pulse when the number of prior write cycles for the memory cell is decreased.

12. The memory device of claim 1 , wherein the memory controller further comprises logic to:
determine the electrical distances between the memory cell and the wordline/bitline decoders within the array of memory cells; and
select the one or more timing offsets for the programming pulse in accordance with the electrical distances between the memory cell and the wordline/bitline decoders being less than a defined threshold or greater than a defined threshold,
wherein the memory cell is a near memory cell when the electrical distances are less than the defined threshold, or the memory cell is a far memory cell when the electrical distances are greater than the defined threshold.

13. The memory device of claim 12 , wherein the memory controller further comprises logic to:
select increased timing offsets for the programming pulse when the electrical distances between the memory cell and the wordline/bitline decoders are less than the defined threshold, indicating that the memory cell is located relatively near from the wordline/bitline decoders; or
select decreased timing offsets for the programming pulse when the electrical distances between the memory cell and the wordline/bitline decoders are greater than the defined threshold, indicating that the memory cell is located relatively far from the wordline/bitline decoders.

14. The memory device of claim 1 , wherein the one or more timing offsets for the programming pulse are variable transition timing offsets that are adjusted based on the polarity of access for the memory cell, the number of prior write cycles for the memory cell, and the electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells.

15. The memory device of claim 1 , wherein the memory controller further comprises logic to reduce a likelihood of program disturbs and reduce a programmability risk in multiple regions of the array of memory cells by selecting optimized timing offsets for programming pulses based on the polarity of access, the number of prior write cycles and the electrical distances for the memory cells being programmed in the array of memory cells.

16. A controller configured to initiate a programming pulse to program a memory cell, the controller comprising logic to:
receive a request to program a memory cell within an array of memory cells in a memory device;
select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells; and
initiate, in response to the request, the programming pulse with the one or more selected timing offsets to program the memory cell within the array of memory cells.

17. The controller of claim 16 , further comprising logic to select the one or more timing offsets between multiple signals of the programming pulse, wherein the multiple signals of the programming pulse include a first signal that corresponds to a path resistance for the memory cell transitioning from high to low, a second signal that corresponds to a voltage bias that is supplied to the memory cell transitioning from low to high, and a third signal that corresponds to a current mirror transitioning from off to on.

18. The controller of claim 16 , further comprising logic to:
determine the polarity of access for the memory cell to be positive when a memory address of the memory cell i

Assignees

• Intel Corp

Inventors

• Banerjee Koushik
• Chu Daniel
• Gottipati Shravya

Classifications

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title