Input/output direct memory access during live memory relocation

Patent metadata

Field	Value
Publication number	US-10552340-B2
Application number	US-201715444795-A
Country	US
Kind code	B2
Filing date	Feb 28, 2017
Priority date	Feb 28, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory including a source region including a plurality of source lines and a destination region including a plurality of destination lines each destination line including one or more status bits;
a cache memory configured to store at least a portion of an address translation map that maps a plurality of logical addresses to a plurality of corresponding physical addresses;
a plurality of registers configured to store a first range of addresses that specifies a source size and a source location of the source region and a second range of addresses that specifies a destination size and a destination location of the destination region; and
a circuit configured to:
perform a relocation operation by copying one or more source lines from the source region to the destination region using an availability of the plurality of destination lines, wherein the availability of the plurality of destination lines is determined using the one or more status bits associated with the destination lines;
in response to receiving, during the relocation operation, a read access request that includes a first logical address, retrieve previously stored data from the source region using a first physical address retrieved from the cache memory using the logical address; and transmit the previously stored data to a device, which originated the read access request;
in response to receiving, during the relocation operation, a write access request that includes new data and a second logical address:
store the new data in a first location in the source region using a second physical address retrieved from the cache memory using the second logical address; and
store the new data in a second location in the destination region corresponding to the first location in the source region.

2. The apparatus of claim 1 , wherein to store the new data in the second location, the circuit is further configured to modify status bits associated with the second location.

3. The apparatus of claim 1 , wherein the circuit is further configured to, in response to a determination that the write access request includes a partial fill write request, merge other data previously stored at the first location with the new data to generate merged data, and store the merged data into the first location and the second location.

4. The apparatus of claim 1 , wherein the one or more status bits are configured to store information indicating a particular destination line is available for read and write access.

5. The apparatus of claim 1 , wherein the circuit is further configured to perform a comparison of the first logical address to a plurality of logical addresses included in the address translation map, and retrieve the first physical address using results of the comparison.

6. The apparatus of claim 1 , wherein the circuit is further configured to, in response to a determination that accesses to the source region are to be mirrored in the destination region, disable the cache memory.

7. A method for operating a computing system, comprising:
initiating a memory relocation operation of data from a source region of a memory included in the computing system to a destination region of the memory, that includes copying one or more source lines from the source region to the destination region using an availability of one or more destination lines included in the destination region, wherein the availability is based on status bits associated with the one or more destination lines;
activating a mirror operation mode in at least one communication circuit included in the computing system in response to initiating the memory relocation operation, wherein accesses to the source region are mirrored to the destination region when the mirror operation mode is active;
in response to receiving from a device, while the mirror operation mode is active, a write access request that include write data and a logical address:
retrieving, using the logical address, a physical address from an address translation cache memory configured to store at least part of an address translation map that maps a plurality of logical addresses to a plurality of corresponding physical addresses; and
storing, by the at least one communication circuit using the physical address, the write data to a line in the source region and a corresponding line in the destination region.

8. The method of claim 7 , wherein activating the mirror operation mode in the at least one communication circuit includes:
blocking, by the at least one communication circuit, at least one new memory access request received from the device;
in response to determining one or more residual transactions have completed, providing information, to the at least one communication circuit, indicative of a source start address of the source region, and a destination start address of the destination region; and
storing a particular value in a control register, in the at least one communication circuit, associated with activating the mirror operation mode.

9. The method of claim 7 , further comprising deactivating the address translation cache memory included in the at least one communication circuit.

10. The method of claim 7 , further comprising, retrieving previously stored data from the source region using the physical address, merging the previously stored data with the write data to generate merged data, and storing the merged data in the line in the source region and the corresponding line in the destination region.

11. The method of claim 7 , further comprising halting the copying of a particular one of the one or more source lines in response to determining that the one or more status bits included in a corresponding destination line indicate the corresponding destination line is read-only.

12. A system, comprising:
an address translation cache memory configured to store at least part of an address map that maps a plurality of logical addresses to a plurality of corresponding physical addresses;
a memory including a source region and a destination region;
a processor configured to, in response to initiating a memory relocation operation, copy one or more source lines from the source region to the destination region using an availability of one or more destination lines included in the destination region, wherein the availability is based on status bits associated with the one or more destination lines;
one or more devices, wherein at least one device of the one or more devices is configured to generate a memory write access request that includes a logical address and write data; and
a communication circuit configured to:
activate a mirror operation mode in response to an initiation the memory relocation operation, wherein accesses to the source region are mirrored to the destination region when the mirror operation mode is active;
in response to receiving, while the mirror operation mode is active, the memory write access request:
retrieve, using the logical address, a physical address from the address translation cache memory; and
store, using the physical address, the write data to a given line in the source region and a corresponding line in the destination region in the memory.

13. The system of claim 12 , wherein to activate the mirror operation mode the communication circuit is further configured to:
block at least one new memory access request received from the at least one device;
receive information indicative of a source start address of the source region, and a destination start address of the destination region;
in response to a determination that one or more residual transactions have completed, st

Assignees

• Oracle Int Corp

Inventors

• Feehrer John
• Stabile Patrick
• Onufer Gregory
• Johnson John

Classifications

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F3/0617

  in relation to availability · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title