Dynamic microsystem reconfiguration with collaborative verification

US10552168B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10552168-B2
Application numberUS-201715605070-A
CountryUS
Kind codeB2
Filing dateMay 25, 2017
Priority dateMay 25, 2017
Publication dateFeb 4, 2020
Grant dateFeb 4, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method dynamically reconfigures a system on a chip (SOC) comprising multiple semiconductor intellectual property (IP) blocks. The method comprises, when booting a data processing system (DPS) comprising the SOC, automatically allocating different IP blocks to multiple different microsystems within the DPS, based on a static partitioning policy (SPP). The method also comprises, after booting the DPS, determining that reallocation of at least one of the IP blocks is desired, based on (a) monitored conditions of at least one of the microsystems and (b) a dynamic partitioning policy (DPP). The method also comprises, in response to determining that reallocation of at least one of the IP blocks is desired, automatically reallocating at least one of the IP blocks from one of the microsystems to another of the microsystems without resetting at least one of the microsystems. Other embodiments are described and claimed.

First claim

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What is claimed is: 1. A data processing system with technology for dynamically reconfiguring a system on a chip, the data processing system comprising: a system on a chip (SOC) with multiple semiconductor intellectual property (IP) blocks, the IP blocks comprising at least one processor; a microsystem manager in the SOC; and nonvolatile storage comprising bootcode and partitioning policies; wherein the bootcode, when executed by the processor to boot the data processing system (DPS), uses the microsystem manager to automatically instantiate multiple different microsystems within the DPS based on the partitioning policies, wherein the multiple different microsystems comprise a management microsystem, a first managed microsystem, and a second managed microsystem; wherein the management microsystem enables to DPS to: automatically determine that reallocation of at least one of the IP blocks is desired, based on (a) monitored conditions of at least one of the microsystems and (b) the partitioning policies; and in response to determining that reallocation of at least one of the IP blocks is desired, automatically reallocate at least one of the IP blocks from the management microsystem to the first managed microsystem without resetting the second managed microsystem. 2. The data processing system according to claim 1 , wherein: the operation of automatically reallocating at least one of the IP blocks further comprises reallocating a specific IP block from the first managed microsystem to the second managed microsystem without resetting the management microsystem. 3. The data processing system according to claim 1 , further comprising: a trusted platform module (TPM); a management module; and at least one default boot module in the bootcode, wherein the at least one default boot module, when executed by the processor to boot the DPS, allocates different IP blocks to the different microsystems; and wherein: the microsystem manager enables the DPS to save at least one measurement for the at least one default boot module in the TPM when the DPS is booting; the management module enables the DPS to create a reconfiguration boot module; the reconfiguration boot module enables the DPS to reallocate at least one of the IP blocks; and the microsystem manager enables the DPS to save a measurement for the reconfiguration boot module in the TPM when the DPS automatically reallocates at least one of the IP blocks from one of the microsystems to another of the microsystems. 4. The data processing system according to claim 3 , wherein: the at least one default boot module enables the DPS to verify at least one measurement for the at least one default boot module when booting the DPS; and the reconfiguration boot module enables to DPS to verify at least one measurement for the reconfiguration boot module when the DPS automatically reallocates at least one of the IP blocks from one of the microsystems to another of the microsystems. 5. The data processing system according to claim 1 , wherein the bootcode enables the DPS to: provide at least one microsystem with a collaboration engine which enables the DPS to use a blockchain to verify whether a proposed reallocation is valid and to archive information identifying verified reallocations. 6. The data processing system according to claim 1 , wherein the bootcode enables the DPS to: provide at least three microsystems with at least three respective collaboration engines, wherein the collaboration engines enable the DPS to: send a measurement for a proposed reallocation to two or more of the collaboration engines; and determine whether a majority of the collaboration engines has verified that the proposed reallocation is valid. 7. The data processing system according to claim 1 , wherein: the bootcode enables the DPS to provide at least two microsystems with at least two respective collaboration engines; and the collaboration engines facilitate communication between the at least two microsystems at runtime. 8. The data processing system according to claim 1 , wherein: the bootcode comprises first and second boot modules which, when executed, instantiate the first and second managed microsystems, respectively; and the operation of automatically reallocating at least one of the IP blocks further comprises: automatically reallocating at least one of the IP blocks from the first managed microsystem to the second managed microsystem without resetting the management microsystem. 9. The data processing system according to claim 1 , wherein: the bootcode comprises first and second boot modules which, when executed, instantiate the first and second managed microsystems, respectively. 10. The data processing system according to claim 1 , wherein: the partitioning policies comprise a static partitioning policy (SPP) and a dynamic partitioning policy (DPP); the SPP prescribes a default configuration of microsystems; and the DPP identifies at least one alternative microsystem configuration as an approved configuration. 11. The data processing system according to claim 10 , wherein the bootcode, when executed by the processor to boot the DPS, automatically allocates different IP blocks to the different microsystems within the DPS, based on the SPP. 12. An apparatus with technology for dynamically reconfiguring a system on a chip, the apparatus comprising: at least one non-transitory machine-accessible storage medium; and bootcode stored at last partially in the at least one machine-accessible medium, wherein the bootcode, when executed by a data processing system (DPS) comprising a microsystem manager, uses the microsystem manager to automatically instantiate multiple different microsystems within the DPS based on partitioning policies, wherein the multiple different microsystems comprise a management microsystem, a first managed microsystem, and a second managed micro system and wherein the operation of automatically instantiating the management microsystem, the first managed microsystem, and the second managed microsystem comprises automatically allocating different semiconductor intellectual property (IP) blocks in a system on a chip (SOC) in the DPS to the management microsystem, the first managed microsystem, and the second managed microsystem; and wherein the management microsystem enables to DPS to: automatically determine, after the DPS has booted, that reallocation of at least one of the IP blocks is desired, based on (a) monitored conditions of at least one of the microsystems and (b) the partitioning policies; and in response to determining that reallocation of at least one of the IP blocks is desired, automatically reallocate at least one of the IP blocks from the management microsystem to the first managed microsystem without resetting the second managed microsystem. 13. The apparatus according to claim 12 , wherein: the bootcode comprises first and second boot modules which, when executed, instantiate the first and second managed microsystems, respectively. 14. The apparatus according to claim 12 , wherein: the bootcode comprises first and second boot modules which, when executed, instantiate the first and second managed microsystems, respectively; and the operation of automatically reallocating at least one of the IP blocks further comprises: automatically reallocating at least one of the IP blocks from the management microsystem to the first managed microsystem without resetting the second managed microsystem. 15. The apparatus according to claim 12 , wherein: the partitioning policies comprise a static partitioning policy (S

Assignees

Inventors

Classifications

  • Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

  • System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

  • with reconfigurable architecture · CPC title

  • Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title

  • G06F9/441Primary

    Multiboot arrangements, i.e. selecting an operating system to be loaded · CPC title

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What does patent US10552168B2 cover?
A method dynamically reconfigures a system on a chip (SOC) comprising multiple semiconductor intellectual property (IP) blocks. The method comprises, when booting a data processing system (DPS) comprising the SOC, automatically allocating different IP blocks to multiple different microsystems within the DPS, based on a static partitioning policy (SPP). The method also comprises, after booting t…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F9/441. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 04 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).