Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-10551952-B2
Application number	US-201715744228-A
Country	US
Kind code	B2
Filing date	Aug 10, 2017
Priority date	Aug 19, 2016
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

An array substrate, a display panel and a display device are disclosed. The array substrate includes a base substrate and common electrode on the base substrate. The common electrode includes a plurality of sub-electrodes in an array, each being used for receiving a common voltage signal and a touch scan signal in a time-sharing manner. The array substrate further includes a common electrode wire corresponding to each sub-electrode. Each sub-electrode receives the common voltage signal through the common electrode wire, and the common electrode wire corresponding to each sub-electrode includes multiple sub-electrode wires, each being connected to the corresponding sub-electrode.

First claim

The invention claimed is:

1. An array substrate, comprising:
a base substrate,
a common electrode on the base substrate, the common electrode including a plurality of sub-electrodes arranged in an array, each sub-electrode being used for receiving a common voltage signal and a touch scan signal in a time-sharing manner, and
a common electrode wire corresponding to each sub-electrode,
wherein each sub-electrode receives the common voltage signal through the common electrode wire, and the common electrode wire comprises multiple sub-electrode wires, each of the multiple sub-electrode wires being connected to the sub-electrode corresponding to the common electrode wire,
wherein the common electrode wire corresponding to each sub-electrode comprises multiple first sub-electrode wires extending in a first direction and multiple second sub-electrode wires extending in a second direction,
wherein for a sub-electrode array arranged along the second direction in the common electrode, the number of the second sub-electrode wires corresponding to the sub-electrodes close to the drive chip is smaller than the number of the second sub-electrode wires corresponding to the sub-electrodes far from the drive chip.

2. The array substrate according to claim 1 , wherein in the common electrode wire corresponding to each sub-electrode, each of the first sub-electrodes wires is connected to one or more second sub-electrode wires.

3. The array substrate according to claim 1 , wherein the array substrate further comprises a gate line and a data line on the base substrate, wherein the first sub-electrode wires and the gate line extend in a same direction and are formed in a same layer with a same material, the second sub-electrode wires and the data line extend in a same direction and formed in a same layer with a same material.

4. The array substrate according to claim 1 , wherein an orthographic projection of the first sub-electrode wire on the base substrate falls within an orthographic projection of the corresponding sub-electrode on the base substrate,
wherein among the multiple second sub-electrode wires corresponding to each of the sub-electrodes, one second sub-electrode wire extends to be connected to a drive chip, while orthographic projections of the rest second sub-electrode wires on the base substrate fall within an orthographic projection of the corresponding sub-electrode on the base substrate, and
wherein the drive chip is used for loading the common voltage signal and the touch scan signal to corresponding sub-electrodes in a time-sharing manner through the second sub-electrode wire connected thereto.

5. The array substrate according to claim 1 , wherein one of the first sub-electrode wire and the second sub-electrode wire has a same extension direction as the gate line in the array substrate, and the other has a same extension direction as the data line in the array substrate.

6. The array substrate according to claim 1 , wherein the array substrate further comprises a plurality of sub-pixels arranged as an array,
wherein two data lines are provided between two adjacent columns of sub-pixels so that each column of sub-pixels is interposed between left data lines and right data lines,
wherein for the data lines at the left and right sides of each column of sub-pixels, one of them is used for driving sub-pixels of odd rows and the other is used for driving sub-pixels of even rows,
wherein one gate line is provided every two rows of sub-pixels, each gate line being used for driving two rows of sub-pixels adjacent thereto.

7. The array substrate according to claim 6 , wherein the first sub-electrodes wire is arranged between two adjacent rows of sub-pixels having no gate line provided therebetween,
wherein the second sub-electrode wire is arranged between the two data lines that are between two adjacent columns of sub-pixels.

8. A display panel, comprising the array substrate according to claim 1 .

9. A display device, comprising the display panel according to claim 8 and a drive chip for providing the common voltage signal and the touch scan signal to the sub-electrodes in a time-sharing manner.

10. The display panel according to claim 8 , wherein the common electrode wire corresponding to each sub-electrode comprises multiple first sub-electrodes wires extending in a first direction and/or multiple second sub-electrode wires extending in a second direction.

11. The display panel according to claim 10 , wherein in the common electrode wire corresponding to each sub-electrode, each of the first sub-electrode wires is connected to one or more second sub-electrode wires.

12. The display panel according to claim 10 , wherein the array substrate further comprises a gate line and a data line on the base substrate, wherein the first sub-electrode wires and the gate line extend in a same direction and are formed in a same layer with a same material, the second sub-electrode wires and the data line extend in a same direction and formed in a same layer with a same material.

13. The display panel according to claim 10 , wherein an orthographic projection of the first sub-electrode wire on the base substrate falls within an orthographic projection of the corresponding sub-electrode on the base substrate,
wherein among the multiple second sub-electrode wires corresponding to each of the sub-electrodes, one second sub-electrode wire extends to be connected to a drive chip, while orthographic projections of the rest second sub-electrode wires on the base substrate fall within an orthographic projection of the corresponding sub-electrode on the base substrate, and
wherein the drive chip is used for loading the common voltage signal and the touch scan signal to corresponding sub-electrodes in a time-sharing manner through the second sub-electrode wire connected thereto.

14. The display panel according to claim 13 wherein for the sub-electrode array arranged along the second direction in the common electrode, the number of the second sub-electrode wires corresponding to the sub-electrodes close to the drive chip is smaller than the number of the second sub-electrode wires corresponding to the sub-electrodes far from the drive chip.

15. The display panel according to claim 14 , wherein one of the first sub-electrode wire and the second sub-electrode wire has a same extension direction as the gate line in the array substrate, and the other has a same extension direction as the data line in the array substrate.

16. The display panel according to claim 10 , wherein the array substrate further comprises a plurality of sub-pixels arranged as an array,
wherein two data lines are provided between two adjacent columns of sub-pixels so that each column of sub-pixels is interposed between left data lines and right data lines,
wherein for the data lines at the left and right sides of each column of sub-pixels, one of them is used for driving sub-pixels of odd rows and the other is used for driving sub-pixels of even rows,
wherein one gate line is provided every two rows of sub-pixels, each gate line being used for driving two rows of sub-pixels adjacent thereto.

17. The display panel according to claim 16 , wherein the first sub-electrode wire is arranged between two adjacent rows of sub-pixels having no gate line provided therebetween,
wherein the second sub-electrode wire is arranged between the two data lines that are between two adjacent columns of sub-pixels.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co
• Beijing Boe Display Tech Group Co Ltd

Inventors

• Wang Xiao

Classifications

• G02F1/13338

  Input devices, e.g. touch panels · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title

• G06F3/0412 Primary

  Digitisers structurally integrated in a display · CPC title