Combining presence detect pin with device management bus reset and power disable

Patent metadata

Field	Value
Publication number	US-10551897-B2
Application number	US-201715719539-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Jun 7, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Provided are devices, systems and methods relating to controller interactions with storage. One embodiment includes an apparatus comprising a controller for communication with a storage device through a signal line, wherein the controller is configured to detect a first signal on the signal line indicating the presence of the storage device on the signal line, and provide a second signal on the signal line to reset the storage device after a detection that the first signal indicates the presence of the storage device. Other embodiments are described and claimed.

First claim

What is claimed:

1. An apparatus comprising:
a controller for communication with a storage device through a signal line;
wherein the controller is configured to:
detect a first signal on the signal line indicating a presence of the storage device on the signal line;
provide a second signal on the signal line to reset the storage device in response to an event, after a detection that the first signal indicates the presence of the storage device, wherein the second signal is held for a first time to reset the storage device; and
wherein the second signal is held for a second time to perform a power down of the storage device.

2. The apparatus of claim 1 , wherein the controller is configured to ignore the presence of the storage device during a time when the controller provides the second signal on the signal line to reset the storage device.

3. The apparatus of claim 1 , further comprising a resistor configured to be in communication with the signal line.

4. The apparatus of claim 3 , further comprising a transistor configured to be in communication with the signal line.

5. A system comprising:
a host;
a controller for communication between the host and a storage device; and
a signal line connecting the controller and the storage device;
wherein the controller is configured to:
detect a first signal on the signal line to indicate a presence of the storage device on the signal line;
provide a second signal on the signal line to reset the storage device in response to an event, after a detection that the first signal indicates the presence of the storage device, wherein the second signal is held for a first time to reset the storage device; and
wherein the second signal is held for a second time to perform a power down of the storage device.

6. The system of claim 5 , wherein the controller is further configured to ignore the presence of the storage device during a time when the controller provides the second signal to reset the storage device.

7. The system of claim 5 , wherein the host includes a first resistor in communication with the signal line, wherein the storage device includes a second resistor in communication with the signal line, and wherein the first resistor has a greater resistance than the second resistor.

8. The system of claim 7 , wherein the host includes a transistor in communication with the signal line.

9. The system of claim 5 , further comprising:
an additional controller for communication between the host and an additional storage device;
an additional signal line to connect the additional controller and the additional storage device;
the additional controller configured to detect a first signal on the additional signal line that indicates a presence of the additional storage device on the additional signal line; and
the additional controller configured to provide a second signal on the additional signal line to reset the additional storage device after a detection that the first signal indicates the presence of the additional storage device.

10. An apparatus comprising:
a storage device for communication with a controller through a signal line;
wherein the storage device is configured so that a first signal is provided on the signal line that indicates a presence of the storage device;
wherein the storage device is configured to receive from the controller a second signal on the signal line to reset the storage device in response to an event, wherein the second signal is held for a first time to reset the storage device; and
wherein the second signal is held for a second time to perform a power down of the storage device.

11. The apparatus of claim 10 , further comprising a resistor in the storage device, the resistor configured to be in communication with the signal line.

12. The storage device of claim 10 , wherein the storage device is configured to power down in response to the signal line holding the second signal for a predetermined amount of time.

13. A method for communicating between a host and a storage device, comprising:
configuring a controller for the host to detect a first signal indicating a presence of the storage device on a signal line between the controller for the host and the storage device;
configuring the controller to reset the storage device in response to an event by providing a second signal on the signal line after detecting the first signal indicating the presence of the storage device, wherein the second signal is held for a first time to reset the storage device; and
configuring the controller so that the second signal is held for a second time to perform a power down of the storage device.

14. The method of claim 13 , further comprising configuring the controller to ignore the presence of the storage device during a time when the controller is providing the second signal to reset the storage device.

15. The method of claim 13 , further comprising configuring the host to include a first resistor in communication with the signal line, and configuring the storage device to include a second resistor in communication with the signal line, wherein the first resistor has a greater resistance than the second resistor.

16. The method of claim 15 , further comprising configuring the host to include a transistor in communication with the signal line.

Assignees

• Intel Corp

Inventors

• Loewen Myron D
• Morning-Smith Andrew W
• Constantine Anthony M

Classifications

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F1/3268

  Power saving in hard disk drive · CPC title

• G06F13/4081

  Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004) · CPC title