Multilayer printed wiring board, and connection structure of multilayer printed wiring board and connector

US10548220B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10548220-B2
Application numberUS-201615180380-A
CountryUS
Kind codeB2
Filing dateJun 13, 2016
Priority dateJun 19, 2015
Publication dateJan 28, 2020
Grant dateJan 28, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer printed wiring board including insulating layers, ground layers thereon, and at least one via hole. The ground layers include a wiring layer and a first impedance adjustment layer. The wiring layer includes a solid conductor and a conductive line. The conductive line is disposed inside an opening and a passage of the solid conductor. The first impedance adjustment layer includes a solid conductor having an opening. The via hole is located inside the openings of the wiring layer and the first impedance adjustment layer and is connected to the conductive line. A first distance is smaller than a second distance, where the first distance is a distance from an outline of the opening of the wiring layer to the via hole, and the second distance is a distance from an outline of the opening of the first impedance adjustment layer to the via hole.

First claim

Opening claim text (preview).

The invention claimed is: 1. A multilayer printed wiring board, comprising: a plurality of insulating layers; a plurality of ground layers on the respective insulating layers, the ground layers including a wiring layer being an upper most layer of the multilayer printed wiring board, a plurality of first impedance adjustment layers, and a connection layer being a lower most layer of the multilayer printed wiring board; and at least one via hole, wherein the wiring layer includes: a solid conductor of the wiring layer, the solid conductor of the wiring layer having an opening and a passage, the passage communicating with the opening, and a conductive line inside the opening and the passage of the wiring layer, each of the first impedance adjustment layers includes a solid conductor of the each first impedance adjustment layer, the solid conductor of the each first impedance adjustment layer having an opening, the connection layer includes a solid conductor of the connection layer, the solid conductor of the connection layer having an opening, the at least one via hole is provided in the insulating layers and the ground layers, the via hole being located inside the opening of the wiring layer, inside the opening of the each first impedance adjustment layer, and inside the opening of the connection layer and being connected to the conductive line, wherein the via hole includes: a hole, a connection conductor of circular tuboid shape provided along a circumference of the hole, a first land inside the opening of the wiring layer, the first land being connected to the connection conductor, a plurality of second lands inside the respective openings of the first impedance adjustment layers, the second lands being connected to the connection conductor, and a land inside the opening of the connection layer, the land inside the opening of the connection layer being connected to the connection conductor, wherein a first distance is a distance in a first direction from an outer periphery of the opening of the wiring layer to the first land of the via hole, and wherein a second distance is a distance, in the same direction as the direction of the first distance, from an outer periphery of the opening of the each first impedance adjustment layer to the second land of the via hole on the same first impedance adjustment layer, the second distance being the same for each of the first impedance adjustment layers, wherein a third distance is a distance, in the same direction as the direction of the first distance, from the outer periphery of the opening of the connection layer to the land of the via hole that is inside the opening of the connection layer, wherein the first distance is smaller than the second distance, and the third distance is smaller than the second distance, wherein the first direction is a plane direction of the multilayer printed wiring board extending radially from the central axis of the via hole, wherein the opening of the wiring layer, the openings of the first impedance adjustment layers, the opening of the connection layer, the first land, the second lands, and the land inside the opening of the connection layers are similar in shape to each other, and wherein inside the opening of the wiring layer there exist no electrically conductive elements other than the first land and the conductive line, and wherein inside the opening of the connection layer there exist no electrically conductive elements other than the land inside the opening of the connection layer. 2. The multilayer printed wiring board according to claim 1 , wherein, each of the second lands is smaller in outside dimension than the first land. 3. The multilayer printed wiring board according to claim 1 , wherein the outer periphery of the opening of the wiring layer is located closer to a central axis of the via hole than the outer periphery of the opening of the each first impedance adjustment layer is. 4. The multilayer printed wiring board according to claim 2 , wherein the outer periphery of the opening of the wiring layer is located closer to a central axis of the via hole than the outer periphery of the opening of the each first impedance adjustment layer is. 5. The multilayer printed wiring board according to claim 2 , wherein the opening of the wiring layer entirely overlaps the opening of the each first impedance adjustment layer in a second direction orthogonal to the first direction. 6. The multilayer printed wiring board according to claim 1 , wherein the ground layers further include a second impedance adjustment layer, wherein the second impedance adjustment layer includes a solid conductor of the second impedance adjustment layer, the solid conductor of the second impedance adjustment layer having an opening, wherein the solid conductor of the second impedance adjustment layer includes an impedance adjustment portion, the impedance adjustment portion overlapping the conductive line of the wiring layer, and wherein the at least one via hole is provided in the ground layers and the insulating layers such as to be located inside the respective openings of the wiring layer, the first impedance adjustment layers, the second impedance adjustment layer, and the connection layer. 7. The multilayer printed wiring board according to claim 6 , wherein at least one of the first impedance adjustment layers is disposed between the wiring layer and the second impedance adjustment layer. 8. The multilayer printed wiring board according to claim 6 , wherein at least one of the first impedance adjustment layers is disposed between the wiring layer and the second impedance adjustment layer and/or between the second impedance adjustment layer and the connection layer. 9. The multilayer printed wiring board according to claim 1 , wherein the second land is smaller in size than the land inside the opening of the connection layer. 10. The multilayer printed wiring board according to claim 1 , wherein the outer periphery of the opening of the connection layer is closer to a central axis of the via hole than the outer periphery of the opening of the each first impedance adjustment layer is. 11. The multilayer printed wiring board according to claim 9 , wherein the opening of the connection layer entirely overlaps the opening of the each first impedance adjustment layer in a second direction orthogonal to the first direction. 12. The multilayer printed wiring board according to claim 1 , wherein the ground layers and the insulating layers are disposed alternately in a second direction orthogonal to the first direction, the wiring layer is one of the ground layers, and each of the first impedance adjustment layers is one of the ground layers excluding the wiring layer. 13. The multilayer printed wiring board according to claim 6 , wherein the ground layers and the insulating layers are disposed alternately in a second direction orthogonal to the first direction, the wiring layer is one of the ground layers, each of the first impedance adjustment layers is one of the ground layers excluding the wiring layer, and the second impedance adjustment layer is one of the ground layers excluding the wiring layer and the first impedance adjustment layers. 14. The multilayer printed wiring board according to claim 8 , wherein the ground layers and the insulating layers are disposed alternately in a second direction orthogonal to the first direction, the wiring layer is one of the ground layers, each of the first impedance adjustment layers is one of the ground layers excluding the wiring layer, and the connection layer is one of the

Assignees

Inventors

Classifications

  • Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • H05K1/116Primary

    Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title

  • H05K1/0251Primary

    related to vias or transitions between vias and transmission lines · CPC title

  • comprising impedance matching means · CPC title

  • terminals for insertion into holes · CPC title

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Frequently asked questions

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What does patent US10548220B2 cover?
A multilayer printed wiring board including insulating layers, ground layers thereon, and at least one via hole. The ground layers include a wiring layer and a first impedance adjustment layer. The wiring layer includes a solid conductor and a conductive line. The conductive line is disposed inside an opening and a passage of the solid conductor. The first impedance adjustment layer includes a …
Who is the assignee on this patent?
Hosiden Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/116. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 28 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).