Variable resistance memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10546999-B2
Application number	US-201615346751-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Feb 17, 2016
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction.

First claim

What is claimed is:

1. A variable resistance memory device, comprising:
first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate;
second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction;
a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a selection pattern, a second electrode, and a variable resistance pattern sequentially stacked such that the second electrode is between the selection pattern and the variable resistance pattern; and
an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including a discontinuous air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction such that no part of the air gap overlaps the first conductive lines or the second conductive lines in the third direction,
wherein:
a bottom of the air gap is higher than upper surfaces of the first conductive lines, a top of the air gap is higher than an upper surface of the second electrode, and the top of the air gap is lower than lower surfaces of the second conductive lines.

2. The variable resistance memory device as claimed in claim 1 , wherein the insulation layer structure includes a first insulation layer between neighboring ones of the memory units in the first direction, the first insulation layer contacting a lower surface of one of the second conductive lines and covering upper sidewalls of the neighboring ones of the memory units.

3. The variable resistance memory device as claimed in claim 2 , comprising a plurality of first insulation layers disposed in the first direction.

4. The variable resistance memory device as claimed in claim 2 , wherein the top of the air gap is lower than a lower surface of the first insulation layer.

5. The variable resistance memory device as claimed in claim 2 , wherein:
a lower surface of the first insulation layer is higher than the upper surface of the second electrode.

6. The variable resistance memory device as claimed in claim 1 , wherein the insulation layer structure:
covers sidewalls of the first and second conductive lines and the memory unit, and includes silicon nitride.

7. The variable resistance memory device as claimed in claim 1 , wherein the insulation layer structure includes:
a first insulation layer covering sidewalls of the first conductive lines; and
a second insulation layer covering sidewalls of the memory units and the second conductive lines.

8. The variable resistance memory device as claimed in claim 7 , wherein:
the first insulation layer includes silicon oxide, and
the second insulation layer includes silicon nitride.

9. The variable resistance memory device as claimed in claim 1 , wherein the memory unit includes a selection pattern, a second electrode, and the variable resistance pattern sequentially stacked.

10. The variable resistance memory device as claimed in claim 9 , further comprising:
a first electrode between each of the first conductive lines and the selection pattern; and
a third electrode between the variable resistance pattern and each of the second conductive lines.

11. The variable resistance memory device as claimed in claim 9 , wherein the selection pattern includes an ovonic threshold switch material containing germanium, silicon, arsenic, or tellurium.

12. The variable resistance memory device as claimed in claim 11 , wherein the selection pattern further includes selenium or sulfur.

13. The variable resistance memory device as claimed in claim 9 , wherein the selection pattern includes at least one selected from the group of AsTeGeSiIn, GeTe, SnTe, GeSe, SnSe, AsTeGeSiSbS, AsTeGeSiIP, AsTeGeSi, As 2 Te 3 Ge, As 2 Se 3 Ge, As 25 (Te 90 Ge 10 ) 75 , Te 40 As 35 Si 18 Ge 6.75 In 0.25 , Te 28 As 34.5 Ge 15.5 S 22 , Te 39 As 36 Si 17 Ge 7 P, As 10 Te 21 S 2 Ge 15 Se 50 Sb 2 , Si 5 Te 34 As 28 Ge 11 S 21 Se 1 , AsTeGeSiSeNS, AsTeGeSiP, AsSe, AsGeSe, AsTeGeSe, ZnTe, GeTePb, GeSeTe, AlAsTe, SeAsGeC, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, GeAsBiSe, or Ge x Se 1-x .

14. The variable resistance memory device as claimed in claim 9 , wherein the second electrode includes carbon or a carbonitride.

15. The variable resistance memory device as claimed in claim 9 , wherein the variable resistance pattern includes a phase-change material.

16. A variable resistance memory device, comprising:
a first memory structure including:
first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate;
second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction;
a first memory unit between the first and second conductive lines, the first memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the first memory unit including a selection pattern, a second electrode, and a first variable resistance pattern sequentially stacked such that the second electrode is between the selection pattern and the first variable resistance pattern; and
a first insulation layer structure between the first and second conductive lines, the first insulation layer structure covering the first memory unit and including a discontinuous first air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction such that no part of the first air gap overlaps the first conductive lines or the second conductive lines in the third direction wherein a bottom of the first air gap is higher than upper surfaces of the first conductive lines, a top of the air gap is higher than an upper surface of the second electrode, and the top of the first air gap is lower than lower surfaces of the second conductive lines; and

a second memory structure on the first memory structure, the second memory structure including:
third conductive lines disposed in the second direction, each of the third conductive lines extending in the first direction;
fourth conductive lines disposed in the first direction over the third conductive lines, each of the fourth conductive lines extending in the second direction;
a second memory unit between the third and fourth conductive lines, the second memory unit being in each area overlapping the third and fourth conductive lines in the third direction, and the second memory unit including a second variable resistance pattern; and
a second insulation layer structure between third and fourth conductive lines, the second insulation layer structure covering the second memory unit and including a discontinuous second air gap in at least a portion of an area overlapping neither the third conductive lines nor the fourth conductive lines in the third direction such that no part of the second air gap overlaps the third conductiv

Assignees

• Samsung Electronics Co Ltd

Inventors

• Terai Masayuki
• Kang Dae-Hwan
• Koh Gwan-Hyeob

Classifications

• H01L45/1233 Primary

  Electricity · mapped topic

• H01L45/143

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic